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T80 Core
by Unknown on May 7, 2008 |
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Hi Andrew,
Things are more like this:
I developed the project first for DE1.
Then, ported to Spartan 3E. I removed the LPM models, and used
Coregen in place.
Almost everything is fine, but, when I add RAM, is messes up both the
RAM and the VRAM. How I can see it does not work? Because I can't read
RAM data anymore, and a working program (which display text on video)
stops from showing the text on video.
I am turning my attention to the clocks now. It may be clock skew issues.
I do not have yet all skills to make a simulation/testbench for this
project, so I am struggling with a trying/error approach to fix this.
I will also take Mike's suggestion, and give a try to the latest T80
release from www.fpgaarcade.com. (Mike, thanks for suggestion, I will
let you know soon how it goes).
Thanks Andrew, and let me know what you think.
----- Original Message -----
From: andrew mulcockspam at m...>
To:
Date: Tue May 6 09:24:21 CEST 2008
Subject: [oc] T80 Core x
I'm impressed you managed to move the Xilinx coregen generated
memory to
Altera tools, if my memory serves me correct, the Xilinx tools
point at some
encrypted file , not the vhdl.
If it works in Altera and not in Xilinx tools, then you could well
have a
porting problem, but in reverse.
Sounds like you generate the code in Xilinx tools, and it did not
work ,
then exported the vhdl to Altera tools, and it did work.
Ok, one last step, new project in Xilinx, and import the Altera
code into
the new project, don't use ANYTHING from the previous Xilinx
project.
Does that 'work'. BTW: how are you certain it does not work ? Any
idea which
part does not work ?
I think into the Altera tools you did not move the encrypted Xilinx
code,
but the modelsim simulation vhdl of the memory, which the Altera
tools then
compiled.
An initial hunch is that the Xilinx tools are being clever, and
knowing
about the core gen stuff, are using one model for simulation one
for
synthesis. Use the vhdl from the working Altera design and that
should force
the Xilinx tools not to be clever and use the 'dum' vhdl as the
Altera tools
did.
If it works, it does not mean the Xilinx tools are at fault
initially, I
just think you might have been trying to out smart them.
Andrew Mulcock
-----Original Message-----
From: cores-bounces at opencores.org [mailto:cores-bounces at
opencores.org] On
Behalf Of ronivon.costa at gmail.com
Sent: 05 May 2008 14:28
To: cores at opencores.org
Subject: [oc] T80 Core x
I would appreciate any help from people who used the T80 core on
this.
This is more a multi-discipline problem, because it relates to Z80
assembly and VHDL:
I have this logic to read/write into memory.
DI_CPU is the Z80 input data bus.
DO_CPU is the Z80 output data bus.
A is the Z80 address bus.
The others signals are for video ram (block memory) and other
devices.
This process is to store data on memory:
writevram: process(Clk_Z80)
begin
if Clk_Z80'event and Clk_Z80 = '1' then
if A >= x"2000" and A http://www.opencores.org/mailman/listinfo/cores No virus found in
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