Hello,

I started my career as a digital designer in the 70's. Back then all
you really needed was a good schematic capture system to enter your
designs. That
lasted until the 90's when chips had grown to the point where you
simply could not plop down gates and hook them up fast enough to meet
a reasonable schedule so we switched to creating the design in RTL and
then synthesizing it into gates.

Well chips haven't stopped growing and we are now approaching the
point were you won't be able to write RTL fast enough to create all
the code that you need to fill a modern asic.

There are a lot of people in the industry trying to figure out the
next big quantum leap that will save us again but so far there is no
agreement as to what that will be.

I would like to start an ongoing discussion on this forum as to what
future ip cores will look like. Hopefully this will lead to a
component design standard and opensource EDA toolsets that could be
used to quickly and easily assemble a group of cores into a working
system.

Most of the cores available on this site are small enough that
RTL/Synthesis still works fine. The problem is that if you want to use
one of these cores in a larger asic then it takes a good deal effort
to figure out where everything is at and what works or doesn't work.

One of the most promising possible solutions is IP-XACT. This is a
soon to be IEEE spec that tells the ip core designer how to design a
core so that it
is (dare I say it?) Plug-and-Play to add it into SOC.

The nice things about this spec is that you really don't have to
change anything that you are already doing. You create a IP-XACT file
that describes your core and include that with your ip. Any IP-XACT
enabled tool can then read your IP and use it.

The file uses XML that is a open format so anyone can write a tool
that can use the information from the IP_XACT file without have to
resort to hand writing your own scripts.

There are commercial ($$$$) tool sets out there using this. I would like
to start creating some opensourced tools that could be used to assemble
opencores ip into SOC's.

Anyone want to help or have any suggestions?

John Eaton

z3qmtr45 at iinet.com wrote: [...]

This is the first time I heard about that (soon to be) standard. Thanks
for sharing that.

I did a quick google search and ran across these slides, explaining a
bit about the standard and a about a Ecplipse plug-in to edit IP-XACT

ftp.osuosl.org/pub/eclipse/dsdp/dd/2007-1-9_Toronto_DD_IP-XACT_Editor_for_Eclipse.ppt

[...]


Maybe the Ecplipse way is a starting point for your idea?

Cheers,

Guenter