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i2c speed - for master core
by Unknown on Jul 9, 2008 |
Not available! | ||
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Hi,
I looked in your i2c master core and according to the spec it is supporting all different speeds - normal,fast and high_speed. One thing that I did not understand is how changing of speed is done in your implementation and how can the user program the master to work in each one of the speeds. Can you elaborate on this? This would help me a lot. Thank you, omer pessach |
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i2c speed - for master core
by Unknown on Jul 9, 2008 |
Not available! | ||
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Mode is just a definition here;
0-100kHz SCL clock: normal 100kHz-400kHz SCL clock: fast 400kHz-(3.5MHz) SCL clock: high speed For the core there's no difference, just program the divider to achieve the desired frequency.
From a pad perspective there might be a difference; Phillips specified a
different pad type for the high speed devices. Although you might achieve
good results using normal pads.
Richard
-----Original Message-----
From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On
Behalf Of omer_pessach at lucidlogix.com
Sent: 09 July 2008 11:13
To: cores at opencores.org
Subject: [oc] i2c speed - for master core
Hi,
I looked in your i2c master core and according to the spec it is
supporting all different speeds - normal,fast and high_speed.
One thing that I did not understand is how changing of speed is done in
your implementation and how can the user program the master to work
in each one of the speeds.
Can you elaborate on this?
This would help me a lot.
Thank you,
omer pessach
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores
|
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i2c speed - for master core
by Unknown on Jul 10, 2008 |
Not available! | ||
|
Hi Richard,
Thank you for your answer.
I just want to make sure I understood this correctly.
Does it mean that for highspeed I need to program the divider after the
arbitration stage(master_code)? - meaning that I need to set EN bit to 0
(disable core) and after that set prescale register again to higher
frequency?
omer
----- Original Message -----
From: Richard Herveillerichard at h...>
To:
Date: Wed Jul 9 17:11:40 CEST 2008
Subject: [oc] i2c speed - for master core
Mode is just a definition here;
0-100kHz SCL clock: normal 100kHz-400kHz SCL clock: fast 400kHz-(3.5MHz) SCL clock: high speed For the core there's no difference, just program the divider to achieve the desired frequency.
>From a pad perspective there might be a difference; Phillips
specified a different pad type for the high speed devices. Although you might achieve good results using normal pads. Richard -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of omer_pessach at lucidlogix.com Sent: 09 July 2008 11:13 To: cores at opencores.org Subject: [oc] i2c speed - for master core Hi, I looked in your i2c master core and according to the spec it is supporting all different speeds - normal,fast and high_speed. One thing that I did not understand is how changing of speed is done in your implementation and how can the user program the master to work
in each one of the speeds.
Can you elaborate on this?
This would help me a lot.
Thank you,
omer pessach
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores
|
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i2c speed - for master core
by Unknown on Jul 11, 2008 |
Not available! | ||
|
If you want to switch modes yes.
However I2C is meant as a suits-all for low speed devices. Simply program
the cores ones such that it works at the most convenient speed for your
connected devices. Note that you cannot use a faster i2c bus than the
slowest device on the bus.
Richard
-----Original Message-----
From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On
Behalf Of omer_pessach at lucidlogix.com
Sent: 10 July 2008 10:48
To: cores at opencores.org
Subject: Re: [oc] i2c speed - for master core
Hi Richard,
Thank you for your answer.
I just want to make sure I understood this correctly.
Does it mean that for highspeed I need to program the divider after the
arbitration stage(master_code)? - meaning that I need to set EN bit to 0
(disable core) and after that set prescale register again to higher
frequency?
omer
----- Original Message -----
From: Richard Herveillerichard at h...>
To:
Date: Wed Jul 9 17:11:40 CEST 2008
Subject: [oc] i2c speed - for master core
Mode is just a definition here;
0-100kHz SCL clock: normal 100kHz-400kHz SCL clock: fast 400kHz-(3.5MHz) SCL clock: high speed For the core there's no difference, just program the divider to achieve the desired frequency.
>From a pad perspective there might be a difference; Phillips
specified a different pad type for the high speed devices. Although you might achieve good results using normal pads. Richard -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of omer_pessach at lucidlogix.com Sent: 09 July 2008 11:13 To: cores at opencores.org Subject: [oc] i2c speed - for master core Hi, I looked in your i2c master core and according to the spec it is supporting all different speeds - normal,fast and high_speed. One thing that I did not understand is how changing of speed is done in your implementation and how can the user program the master to work
in each one of the speeds.
Can you elaborate on this?
This would help me a lot.
Thank you,
omer pessach
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores
|
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i2c speed - for master core
by Unknown on Aug 4, 2008 |
Not available! | ||
|
Hi Richard,
Is there an option to control setup and hold time of the master?
I want to change them in order to examine slave behaviour.
thank you,
omer
----- Original Message -----
From: Richard Herveillerichard at h...>
To:
Date: Fri Jul 11 05:47:51 CEST 2008
Subject: [oc] i2c speed - for master core
If you want to switch modes yes.
However I2C is meant as a suits-all for low speed devices. Simply
program
the cores ones such that it works at the most convenient speed for
your
connected devices. Note that you cannot use a faster i2c bus than
the
slowest device on the bus.
Richard
-----Original Message-----
From: cores-bounces at opencores.org [mailto:cores-bounces at
opencores.org] On
Behalf Of omer_pessach at lucidlogix.com
Sent: 10 July 2008 10:48
To: cores at opencores.org
Subject: Re: [oc] i2c speed - for master core
Hi Richard,
Thank you for your answer.
I just want to make sure I understood this correctly.
Does it mean that for highspeed I need to program the divider after
the
arbitration stage(master_code)? - meaning that I need to set EN bit
to 0
(disable core) and after that set prescale register again to higher
frequency?
omer
----- Original Message -----
From: Richard Herveille
To:
Date: Wed Jul 9 17:11:40 CEST 2008
Subject: [oc] i2c speed - for master core
> Mode is just a definition here;
> 0-100kHz SCL clock: normal > 100kHz-400kHz SCL clock: fast > 400kHz-(3.5MHz) SCL clock: high speed > For the core there's no difference, just program the divider to
> achieve the
> desired frequency.
>From a pad perspective there might be a difference;
Phillips
> specified a
> different pad type for the high speed devices. Although you might
> achieve
> good results using normal pads. > Richard > -----Original Message----- > From: cores-bounces at opencores.org [mailto:cores-bounces at > opencores.org] On > Behalf Of omer_pessach at lucidlogix.com > Sent: 09 July 2008 11:13 > To: cores at opencores.org > Subject: [oc] i2c speed - for master core > Hi, > I looked in your i2c master core and according to the spec it is
> supporting all different speeds - normal,fast and high_speed.
> One thing that I did not understand is how changing of speed is
> done in
> your implementation and how can the user program the master to work
> in each one of the speeds.
> Can you elaborate on this?
> This would help me a lot.
> Thank you,
> omer pessach
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
>
>
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores
|
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i2c speed - for master core
by Unknown on Aug 5, 2008 |
Not available! | ||
|
Setup and hold time ... You mean the timing relationship between SCL and
SDA?
That is fixed in the i2c_bit_control statemachine.
Unless you modify that statemachine you cannot change the timing relation.
Richard
-----Original Message-----
From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On
Behalf Of omer_pessach at lucidlogix.com
Sent: 04 August 2008 10:27
To: cores at opencores.org
Subject: Re: [oc] i2c speed - for master core
Hi Richard,
Is there an option to control setup and hold time of the master?
I want to change them in order to examine slave behaviour.
thank you,
omer
----- Original Message -----
From: Richard Herveillerichard at h...>
To:
Date: Fri Jul 11 05:47:51 CEST 2008
Subject: [oc] i2c speed - for master core
If you want to switch modes yes.
However I2C is meant as a suits-all for low speed devices. Simply
program
the cores ones such that it works at the most convenient speed for
your
connected devices. Note that you cannot use a faster i2c bus than
the
slowest device on the bus.
Richard
-----Original Message-----
From: cores-bounces at opencores.org [mailto:cores-bounces at
opencores.org] On
Behalf Of omer_pessach at lucidlogix.com
Sent: 10 July 2008 10:48
To: cores at opencores.org
Subject: Re: [oc] i2c speed - for master core
Hi Richard,
Thank you for your answer.
I just want to make sure I understood this correctly.
Does it mean that for highspeed I need to program the divider after
the
arbitration stage(master_code)? - meaning that I need to set EN bit
to 0
(disable core) and after that set prescale register again to higher
frequency?
omer
----- Original Message -----
From: Richard Herveille
To:
Date: Wed Jul 9 17:11:40 CEST 2008
Subject: [oc] i2c speed - for master core
> Mode is just a definition here;
> 0-100kHz SCL clock: normal > 100kHz-400kHz SCL clock: fast > 400kHz-(3.5MHz) SCL clock: high speed > For the core there's no difference, just program the divider to
> achieve the
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores
> desired frequency.
>From a pad perspective there might be a difference;
Phillips
> specified a
> different pad type for the high speed devices. Although you might
> achieve
> good results using normal pads. > Richard > -----Original Message----- > From: cores-bounces at opencores.org [mailto:cores-bounces at > opencores.org] On > Behalf Of omer_pessach at lucidlogix.com > Sent: 09 July 2008 11:13 > To: cores at opencores.org > Subject: [oc] i2c speed - for master core > Hi, > I looked in your i2c master core and according to the spec it is
> supporting all different speeds - normal,fast and high_speed.
> One thing that I did not understand is how changing of speed is
> done in
> your implementation and how can the user program the master to work
> in each one of the speeds.
> Can you elaborate on this?
> This would help me a lot.
> Thank you,
> omer pessach
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
>
>
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores
|
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