Fabrizio Fazzino wrote:
To make a long story short, on Debian/Ubuntu: sudo apt-get purge verilog sudo apt-get install git-core autoconf gperf flex bison git clone git://icarus.com/~steve-icarus/verilog cd verilog source autoconf.sh ./configure make make install Thanks to Steve Williams this new version of Icarus now compiles Verilog generate constructs. Thanks Steve! Fabrizio ========================================== Fabrizio Fazzino fabrizio at fazzino.it http://www.fazzino.it/ Simply RISC fabrizio.fazzino at srisc.com http://www.srisc.com/ University of Catania fabrizio.fazzino at diit.unict.it http://www.diit.unict.it/users/ffazzino/ ========================================== -- > Occam's Razor (XIV century)

Alessandro, MikeJ,

has anybody been successful in implementing a DDR SDRAM controller for
the S3e SK? I spent 2 month on that now, and although I have it right
in the behavioral simulation, the best I get from hardware is 1 out of
2 words read correct. I guess I just cannot get the timing constraints
right.

If you had more success I'd like to hear from you.

Klaus, The Plasma CPU uses the Xilinx Spartan-3E Starter Kit with a DDR controller. See http://www.opencores.org/projects.cgi/web/mips/overview It running a live Web Server at: http://plasmacpu.no-ip.org:8080/ To keep the DDR controller simple, it takes a 50 MHz clock and acceses the DDR at 25 MHz. You need ddr_ctrl.vhd and ddr_init.c. Steve Rhoads ----- Original Message ----- From: Klaus.Rindtorff at googlemail.comKlaus.Rindtorff at g...> To: Date: Sat Sep 6 22:05:35 CEST 2008 Subject: [oc] DDR IP for Spartan 3E Xilinx evakit

I have it working now. Turned out that the READs were (almost) ok, but
the WRITE operation was wrong. I had to increase the duration where
the DQ and DQS were enabled significantly. Next step is to run a few
memory tests to check how stable it is at 100MHz.