Hi everybody! I'm working at this enhanced ZX-Spectrum clone (ZX-Badaloc) project: http://www.zxbada.bbk.org/badaloc_fpga/index.htm and, thanks to the support about the T80 core of Mike Johnson, who suggested a workaround for timing problem (using the fpgaarcade's pacman T80 wrapper), it is possible to run the clone on the Spartan 3E evaluation board (downloadable file available). I'm using the internal blockram of the fpga, but the next step would be accessing the on-board DDR chip and to implement all the advanced memory features of the original clone (that I made using a XPLA3 cpld a couple of years ago). The problem is: is there a way to istantiate a DDR controller which matches the ddr chip installed on this board without getting mad? I've been trying in many ways; maybe I need to install the EDK that comes with the board, but the problem is: I started the project on ISE 10 and I don't want to downgrade it to 9 (which is the version of EDK on my Xilinx DVD). Furthermore, I'm not even sure this would solve the problem. I'm new to fpgas, I found a way to istantiate block ram, the DCM for 85MHz, the T80 processor... but this time I'm stuck. I see there are ddr controller's IP here and there but it seems a complex matter to me. I can't believe xilinx does not provide one ready to use for this board... am I wrong? If someone could help me, we may see a 64megabyte 42.5MHz ZX-Spectrum soon :-) Thanks in advance and Best Regards Alessandro

And I'd imagine the Edk you have on disk is an eval version, they normally are as EDK costs extra. If you did pay for EDK, then you get one year of update, so you could then update to latest EDK. Xilinx certainly used to provide BDF's, for instance this is the link to the reference designs for one of the Xilinx boards I use. http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm Andrew -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of Alessandro Sent: 10 July 2008 22:23 To: Discussion list about free open source IP cores Subject: [oc] DDR IP for Spartan 3E Xilinx evakit Hi everybody! I'm working at this enhanced ZX-Spectrum clone (ZX-Badaloc) project: http://www.zxbada.bbk.org/badaloc_fpga/index.htm and, thanks to the support about the T80 core of Mike Johnson, who suggested a workaround for timing problem (using the fpgaarcade's pacman T80 wrapper), it is possible to run the clone on the Spartan 3E evaluation board (downloadable file available). I'm using the internal blockram of the fpga, but the next step would be accessing the on-board DDR chip and to implement all the advanced memory features of the original clone (that I made using a XPLA3 cpld a couple of years ago). The problem is: is there a way to istantiate a DDR controller which matches the ddr chip installed on this board without getting mad? I've been trying in many ways; maybe I need to install the EDK that comes with the board, but the problem is: I started the project on ISE 10 and I don't want to downgrade it to 9 (which is the version of EDK on my Xilinx DVD). Furthermore, I'm not even sure this would solve the problem. I'm new to fpgas, I found a way to istantiate block ram, the DCM for 85MHz, the T80 processor... but this time I'm stuck. I see there are ddr controller's IP here and there but it seems a complex matter to me. I can't believe xilinx does not provide one ready to use for this board... am I wrong? If someone could help me, we may see a 64megabyte 42.5MHz ZX-Spectrum soon :-) Thanks in advance and Best Regards Alessandro _______________________________________________ http://www.opencores.org/mailman/listinfo/cores No virus found in this incoming message. Checked by AVG. Version: 8.0.100 / Virus Database: 270.4.7/1542 - Release Date: 09/07/2008 06:50

Hi Alessandro, we have the same goal: using the DDR SDRAM on the S3E
board. So far I am trying to make the Opencores DDR_SDR core from this
site work for me. Writes are ok, but I still have problems with reads
in some circumstances. Your other option would be to use MIG from the
ISE SDK to generate a core for you. I didn't try that yet as the
generated core looks too complicated to me.

The Plasma CPU also has a simple DDR SDRAM controller for the Spartan
3E Xilinx evaluation board.

Steve Rhoads
Plasma CPU Maintainer

----- Original Message ----- From: Klaus.Rindtorff at googlemail.comKlaus.Rindtorff at g...> To: Date: Mon Jul 28 08:31:16 CEST 2008 Subject: [oc] DDR IP for Spartan 3E Xilinx evakit

IC... I'm new to DDR and it seems critical.

Your other option would be to use MIG from


Too complicated to me too! When I generated the source code, I could
not believe it! It's larger than the whole project :-) definitely too
complicated.

Ciao!
Alessandro

----- Original Message ----- From: rhoads at opencores.orgrhoads at o...> To: Date: Wed Jul 30 03:46:17 CEST 2008 Subject: [oc] DDR IP for Spartan 3E Xilinx evakit

Thanks, I'm browsing the file and it looks far more "usable" than
those generated by MIG. My bus width is 8 bits instead of 32 (I see
you double-read the chip to build the needed 32 bits for your
processor) and there are a few points I need to dig to understand, but
it will certainly help. Will it work if the base frequency differs
from what you need? I have a 85MHz (dcm generated) so I may clock the
component at 42.5 and provide the x2 clock at 85.

MikeJ of fpgaarcade is also writing a ddr controller... it seems ddr
are widely used.

Ciao!
Alessandro

Read for ddr is little complex,
you should check the data path,
maybe timing for logic is OK,(I didn't read code yet)
In FPGA your also need to check detail timing , ucf ,etc.
On chip debug is via by chipscope from Xilinx.

Good Luck.

Hi Steve, many thanks. I will give your code a try immediately.
Is there a description of the mem_ctrl interface signals available?

When looking at the implementation I am missing the typical 200 us
wait for the SDRAM, but found a reference to DdrInit(). I guess that
means that the CPU is responsible to create a memory access pattern
during startup that will initialize the chip, correct?

- Klaus

Alessandro, Klaus, Hi,

Did you try the controller at https://roulette.das-labor.org/bzrtrac/wiki/wb_ddr ?? I had positive feedback from some people who got it work without major glitches. j.

Hi Jörg, I'd love to use your controller, but it is written in
Verilog. I just got used to VHDL and don't want to switch back. I
believe I saw a VHDL version in your download section some month ago,
but it seems they it was removed since then.
This is so frustrating: I have a working CPU and tool-chain in my
software simulation, but mess around with the DDR memory of the Xilinx
S3E board for months now...

Jörg Bornschein jb at capsec.org>:


Hi Joerg,
I found your DDR interfaces very interesting; I started from the (relatively
simpler) core named "ddr_ctrl" on your site, but your simulation Makefile
crashes with Icarus Verilog complaining with "genvar" and "generate"
Verilog commands.

I'm using Ubuntu with Icarus version 0.8.5-1 and it seems that the "generate"
commands should be supported, any idea why it does not recognize them?

Thanks in advance,

Fabrizio

Fabrizio Fazzino wrote:

I'm using Ubunntu too, but running a recent git checkout of iverilog (git clone git://icarus.com/~steve-icarus/verilog). The git version also fixes some fatal bugs which did not allow mico32 to be simulated.... I _thought_ the version Ubuntu 8.04 is shipping is adequatly current -- obviously not. I'll update the webpage. j.

On Saturday, August 09, 2008 10:42 PM [GMT+1=CET], Fabrizio Fazzino fabrizio at fazzino.it> wrote:

Why am I unable to open this link?

Ciao!
Alessandro

Alessandro wrote:
Maybe you are using Firefox 3 or another browser with too strong security checks enabled... try the normal http access instead: http://roulette.das-labor.org/bzrtrac/wiki/wb_ddr Ciao, Fabrizio ========================================== Fabrizio Fazzino fabrizio at fazzino.it http://www.fazzino.it/ Simply RISC fabrizio.fazzino at srisc.com http://www.srisc.com/ University of Catania fabrizio.fazzino at diit.unict.it http://www.diit.unict.it/users/ffazzino/ ========================================== -- > Occam's Razor (XIV century)

Joerg Bornschein ha scritto:
Following your suggestion and the instruction from http://iverilog.wikia.com/wiki/Installation_Guide#Installation_From_Source I installed the development version of Icarus and I was able to compile your DDR Controller just out-of-the-box. In the next few days I'll try to merge it into the M1 Core design to try it on the Spartan-3E Starter Kit: http://opencores.org/projects.cgi/web/m1_core/overview Many thanks, Fabrizio ========================================== Fabrizio Fazzino fabrizio at fazzino.it http://www.fazzino.it/ Simply RISC fabrizio.fazzino at srisc.com http://www.srisc.com/ University of Catania fabrizio.fazzino at diit.unict.it http://www.diit.unict.it/users/ffazzino/ ========================================== -- > Occam's Razor (XIV century)