1/1 
|
How do YOU implement WISHBONE regs' access and why?
by Unknown on Jul 30, 2008 |
Not available! | ||
|
Hello everybody,
Usually in my projects I avoid complications when implementing the Wishbone bus and regs by using a double port memory (DP-RAM) to store the reg contents: one port for the WB bus and the other for my core's exclusive use. I recently studied the Ethernet core and saw an interesting solution there, where a single port dist. ram (SP-RAM) was used and a state machine was set up for up to three processes to use the single port (the WB bus itself and two other core's processes). As far as I can tell, the SP-RAM solution uses a simpler RAM, it's sure there won't be any concurrent writes to the same reg, but needs a state machine and one can not make any assumptions about a fixed time to read its contents. On the other side the DP-RAM solution is way simpler (doesn't need the arbiter state machine) and gives exclusive access to the WB bus and to the core, but could run into problems with concurrent writes to the same register. Now I think it interesting to know and share with the community: How do you implement this in your cores and why? Do you see any other problems that could arise from these solutions? Best regards! Victor Lopez |
|||
|
How do YOU implement WISHBONE regs' access and why?
by Unknown on Jul 31, 2008 |
Not available! | ||
|
This depends on the amount of registers you need.
Most of my cores use true register banks as they only need a few
command/status registers.
For cores with large memory requirements (e.g. color luts) I use single port
memories.
For ASIC implementations you definitely want SP instead of 2P or even DP
memories, simply due to the increased size of these. Two port and dual port
memories require almost twice the silicon area compared to single port
memories.
Richard
-----Original Message-----
From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On
Behalf Of VÃctor López
Sent: 30 July 2008 16:49
To: Discussion list about free open source IP cores
Subject: [oc] How do YOU implement WISHBONE regs' access and why?
Hello everybody,
Usually in my projects I avoid complications when implementing the
Wishbone bus and regs by using a double port memory (DP-RAM) to store
the reg contents: one port for the WB bus and the other for my core's
exclusive use.
I recently studied the Ethernet core and saw an interesting solution
there, where a single port dist. ram (SP-RAM) was used and a state
machine was set up for up to three processes to use the single port (the
WB bus itself and two other core's processes).
As far as I can tell, the SP-RAM solution uses a simpler RAM, it's
sure there won't be any concurrent writes to the same reg, but needs a
state machine and one can not make any assumptions about a fixed time to
read its contents. On the other side the DP-RAM solution is way simpler
(doesn't need the arbiter state machine) and gives exclusive access to
the WB bus and to the core, but could run into problems with concurrent
writes to the same register.
Now I think it interesting to know and share with the community: How
do you implement this in your cores and why? Do you see any other
problems that could arise from these solutions?
Best regards!
Victor Lopez
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores
|
|||
|
How do YOU implement WISHBONE regs' access and why?
by Unknown on Aug 2, 2008 |
Not available! | ||
|
Richard, what you said about ASIC silicon usage was very interesting, I
am way too biased by FPGAs and have almost no experience designing towards ASIC targets, could you recommend a good book/manual/tutorial about ASIC design's 'best practices'? Thanks! Victor Richard Herveille escribió:
This depends on the amount of registers you need.
Most of my cores use true register banks as they only need a few
command/status registers.
For cores with large memory requirements (e.g. color luts) I use single port
memories.
For ASIC implementations you definitely want SP instead of 2P or even DP
memories, simply due to the increased size of these. Two port and dual port
memories require almost twice the silicon area compared to single port
memories.
Richard
-----Original Message-----
From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On
Behalf Of VÃctor López
Sent: 30 July 2008 16:49
To: Discussion list about free open source IP cores
Subject: [oc] How do YOU implement WISHBONE regs' access and why?
Hello everybody,
Usually in my projects I avoid complications when implementing the
Wishbone bus and regs by using a double port memory (DP-RAM) to store
the reg contents: one port for the WB bus and the other for my core's
exclusive use.
I recently studied the Ethernet core and saw an interesting solution
there, where a single port dist. ram (SP-RAM) was used and a state
machine was set up for up to three processes to use the single port (the
WB bus itself and two other core's processes).
As far as I can tell, the SP-RAM solution uses a simpler RAM, it's
sure there won't be any concurrent writes to the same reg, but needs a
state machine and one can not make any assumptions about a fixed time to
read its contents. On the other side the DP-RAM solution is way simpler
(doesn't need the arbiter state machine) and gives exclusive access to
the WB bus and to the core, but could run into problems with concurrent
writes to the same register.
Now I think it interesting to know and share with the community: How
do you implement this in your cores and why? Do you see any other
problems that could arise from these solutions?
Best regards!
Victor Lopez
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores
|
|||
1/1