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i2c - suspected wrong behaviour + timing issue

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i2c - suspected wrong behaviour + timing issue by Unknown on Aug 5, 2008			Not available!
Hi Richard, I have two issues i wanted your help. 1. When using your master with prescale >= 16'h0040 (scl =~260 KHZ) with real slave everything is working great, but when I am configuring your master with lower prescale,for example 16'0030 (meaning higher freq) the master is not working propertly -> i2c_al is asserted after 2 clks . Why is that ? (according to spec core suppose to work also in high speed) 2. Is there a way that i can change setup and hold time of master? thank you, omer Hi Richard, I have two issues i wanted your help. 1. When using your master with prescale >= 16'h0040 (scl =~260 KHZ) with real slave everything is working great, but when I am configuring your master with lower prescale,for example 16'0030 (meaning higher freq) the master is not working propertly -> i2c_al is asserted after 2 clks . Why is that ? (according to spec core suppose to work also in high speed) 2. Is there a way that i can change setup and hold time of master? thank you, omer

i2c - suspected wrong behaviour + timing issue by Unknown on Aug 5, 2008			Not available!
Does your slave support this higher speed as well? Arbitration lost is generated when the i2c-master wants to drive SDA high, but somebody else is driving it low. If your slave cannot handle the higher speed or the slew on the PCB tracks is too much (i.e. too slow signal transitions) then it triggers arbitration lost. Richard -----Original Message----- From: <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores-bounces at opencores.org</A> [mailto:<A HREF="http://www.opencores.org/mailman/listinfo/cores">cores-bounces at opencores.org</A>] On Behalf Of <A HREF="http://www.opencores.org/mailman/listinfo/cores">omer_pessach at lucidlogix.com</A> Sent: 05 August 2008 10:20 To: <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at opencores.org</A> Subject: [oc] i2c - suspected wrong behaviour + timing issue Hi Richard, I have two issues i wanted your help. 1. When using your master with prescale >= 16'h0040 (scl =~260 KHZ) with real slave everything is working great, but when I am configuring your master with lower prescale,for example 16'0030 (meaning higher freq) the master is not working propertly -> i2c_al is asserted after 2 clks . Why is that ? (according to spec core suppose to work also in high speed) 2. Is there a way that i can change setup and hold time of master? thank you, omer _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> Does your slave support this higher speed as well? Arbitration lost is generated when the i2c-master wants to drive SDA high, but somebody else is driving it low. If your slave cannot handle the higher speed or the slew on the PCB tracks is too much (i.e. too slow signal transitions) then it triggers arbitration lost. Richard -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of omer_pessach at lucidlogix.com Sent: 05 August 2008 10:20 To: cores at opencores.org Subject: [oc] i2c - suspected wrong behaviour + timing issue Hi Richard, I have two issues i wanted your help. 1. When using your master with prescale >= 16'h0040 (scl =~260 KHZ) with real slave everything is working great, but when I am configuring your master with lower prescale,for example 16'0030 (meaning higher freq) the master is not working propertly -> i2c_al is asserted after 2 clks . Why is that ? (according to spec core suppose to work also in high speed) 2. Is there a way that i can change setup and hold time of master? thank you, omer _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

i2c - suspected wrong behaviour + timing issue by Unknown on Aug 6, 2008			Not available!
Thank you for your answers, I will recheck my design. omer ----- Original Message ----- From: Richard Herveille<<A HREF="http://www.opencores.org/mailman/listinfo/cores">richard at h...</A>> To: Date: Tue Aug 5 10:46:59 CEST 2008 Subject: [oc] i2c - suspected wrong behaviour + timing issue [q] Does your slave support this higher speed as well? Arbitration lost is generated when the i2c-master wants to drive SDA high, but somebody else is driving it low. If your slave cannot handle the higher speed or the slew on the PCB tracks is too much (i.e. too slow signal transitions) then it triggers arbitration lost. Richard -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of omer_pessach at lucidlogix.com Sent: 05 August 2008 10:20 To: cores at opencores.org Subject: [oc] i2c - suspected wrong behaviour + timing issue Hi Richard, I have two issues i wanted your help. 1. When using your master with prescale >= 16'h0040 (scl =~260 KHZ) with real slave everything is working great, but when I am configuring your master with lower prescale,for example 16'0030 (meaning higher freq) the master is not working propertly -> i2c_al is asserted after 2 clks . Why is that ? (according to spec core suppose to work also in high speed) 2. Is there a way that i can change setup and hold time of master? thank you, omer _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> [/q] Thank you for your answers, I will recheck my design. omer ----- Original Message ----- From: Richard Herveillerichard at h...> To: Date: Tue Aug 5 10:46:59 CEST 2008 Subject: [oc] i2c - suspected wrong behaviour + timing issue Does your slave support this higher speed as well? Arbitration lost is generated when the i2c-master wants to drive SDA high, but somebody else is driving it low. If your slave cannot handle the higher speed or the slew on the PCB tracks is too much (i.e. too slow signal transitions) then it triggers arbitration lost. Richard -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of omer_pessach at lucidlogix.com Sent: 05 August 2008 10:20 To: cores at opencores.org Subject: [oc] i2c - suspected wrong behaviour + timing issue Hi Richard, I have two issues i wanted your help. 1. When using your master with prescale >= 16'h0040 (scl =~260 KHZ) with real slave everything is working great, but when I am configuring your master with lower prescale,for example 16'0030 (meaning higher freq) the master is not working propertly -> i2c_al is asserted after 2 clks . Why is that ? (according to spec core suppose to work also in high speed) 2. Is there a way that i can change setup and hold time of master? thank you, omer _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

i2c - suspected wrong behaviour + timing issue by omer on Aug 6, 2008			omer Posts: 2 Joined: Jun 12, 2008 Last seen: Aug 6, 2008
Hi Richard, I saw that in tst_bench_top.v there is a delay of 600 (appears to be ns). When working in high frequency with this delay al signal is asserted and only when reducing tjhis delay to 300 it seems to work. What is this delay supposed to model ? because if it is hold time then it is too much than spec ? please advice, thank you omer ----- Original Message ----- From: Richard Herveille<<A HREF="http://www.opencores.org/mailman/listinfo/cores">richard at h...</A>> To: Date: Tue Aug 5 10:46:59 CEST 2008 Subject: [oc] i2c - suspected wrong behaviour + timing issue [q] Does your slave support this higher speed as well? Arbitration lost is generated when the i2c-master wants to drive SDA high, but somebody else is driving it low. If your slave cannot handle the higher speed or the slew on the PCB tracks is too much (i.e. too slow signal transitions) then it triggers arbitration lost. Richard -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of omer_pessach at lucidlogix.com Sent: 05 August 2008 10:20 To: cores at opencores.org Subject: [oc] i2c - suspected wrong behaviour + timing issue Hi Richard, I have two issues i wanted your help. 1. When using your master with prescale >= 16'h0040 (scl =~260 KHZ) with real slave everything is working great, but when I am configuring your master with lower prescale,for example 16'0030 (meaning higher freq) the master is not working propertly -> i2c_al is asserted after 2 clks . Why is that ? (according to spec core suppose to work also in high speed) 2. Is there a way that i can change setup and hold time of master? thank you, omer _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> [/q] Hi Richard, I saw that in tst_bench_top.v there is a delay of 600 (appears to be ns). When working in high frequency with this delay al signal is asserted and only when reducing tjhis delay to 300 it seems to work. What is this delay supposed to model ? because if it is hold time then it is too much than spec ? please advice, thank you omer ----- Original Message ----- From: Richard Herveillerichard at h...> To: Date: Tue Aug 5 10:46:59 CEST 2008 Subject: [oc] i2c - suspected wrong behaviour + timing issue Does your slave support this higher speed as well? Arbitration lost is generated when the i2c-master wants to drive SDA high, but somebody else is driving it low. If your slave cannot handle the higher speed or the slew on the PCB tracks is too much (i.e. too slow signal transitions) then it triggers arbitration lost. Richard -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of omer_pessach at lucidlogix.com Sent: 05 August 2008 10:20 To: cores at opencores.org Subject: [oc] i2c - suspected wrong behaviour + timing issue Hi Richard, I have two issues i wanted your help. 1. When using your master with prescale >= 16'h0040 (scl =~260 KHZ) with real slave everything is working great, but when I am configuring your master with lower prescale,for example 16'0030 (meaning higher freq) the master is not working propertly -> i2c_al is asserted after 2 clks . Why is that ? (according to spec core suppose to work also in high speed) 2. Is there a way that i can change setup and hold time of master? thank you, omer _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

i2c - suspected wrong behaviour + timing issue by Unknown on Aug 6, 2008			Not available!
The 600ns delay is the max.delay (for fast speed??) as defined by the i2c specs. Richard -----Original Message----- From: <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores-bounces at opencores.org</A> [mailto:<A HREF="http://www.opencores.org/mailman/listinfo/cores">cores-bounces at opencores.org</A>] On Behalf Of <A HREF="http://www.opencores.org/mailman/listinfo/cores">omer at lucidlogix.com</A> Sent: 06 August 2008 16:35 To: <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at opencores.org</A> Subject: Re: [oc] i2c - suspected wrong behaviour + timing issue Hi Richard, I saw that in tst_bench_top.v there is a delay of 600 (appears to be ns). When working in high frequency with this delay al signal is asserted and only when reducing tjhis delay to 300 it seems to work. What is this delay supposed to model ? because if it is hold time then it is too much than spec ? please advice, thank you omer ----- Original Message ----- From: Richard Herveille<<A HREF="http://www.opencores.org/mailman/listinfo/cores">richard at h...</A>> To: Date: Tue Aug 5 10:46:59 CEST 2008 Subject: [oc] i2c - suspected wrong behaviour + timing issue [q] Does your slave support this higher speed as well? Arbitration lost is generated when the i2c-master wants to drive SDA high, but somebody else is driving it low. If your slave cannot handle the higher speed or the slew on the PCB tracks is too much (i.e. too slow signal transitions) then it triggers arbitration lost. Richard -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of omer_pessach at lucidlogix.com Sent: 05 August 2008 10:20 To: cores at opencores.org Subject: [oc] i2c - suspected wrong behaviour + timing issue Hi Richard, I have two issues i wanted your help. 1. When using your master with prescale >= 16'h0040 (scl =~260 KHZ) with real slave everything is working great, but when I am configuring your master with lower prescale,for example 16'0030 (meaning higher freq) the master is not working propertly -> i2c_al is asserted after 2 clks . Why is that ? (according to spec core suppose to work also in high speed) 2. Is there a way that i can change setup and hold time of master? thank you, omer _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> [/q] _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> The 600ns delay is the max.delay (for fast speed??) as defined by the i2c specs. Richard -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of omer at lucidlogix.com Sent: 06 August 2008 16:35 To: cores at opencores.org Subject: Re: [oc] i2c - suspected wrong behaviour + timing issue Hi Richard, I saw that in tst_bench_top.v there is a delay of 600 (appears to be ns). When working in high frequency with this delay al signal is asserted and only when reducing tjhis delay to 300 it seems to work. What is this delay supposed to model ? because if it is hold time then it is too much than spec ? please advice, thank you omer ----- Original Message ----- From: Richard Herveillerichard at h...> To: Date: Tue Aug 5 10:46:59 CEST 2008 Subject: [oc] i2c - suspected wrong behaviour + timing issue Does your slave support this higher speed as well? Arbitration lost is generated when the i2c-master wants to drive SDA high, but somebody else is driving it low. If your slave cannot handle the higher speed or the slew on the PCB tracks is too much (i.e. too slow signal transitions) then it triggers arbitration lost. Richard -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of omer_pessach at lucidlogix.com Sent: 05 August 2008 10:20 To: cores at opencores.org Subject: [oc] i2c - suspected wrong behaviour + timing issue Hi Richard, I have two issues i wanted your help. 1. When using your master with prescale >= 16'h0040 (scl =~260 KHZ) with real slave everything is working great, but when I am configuring your master with lower prescale,for example 16'0030 (meaning higher freq) the master is not working propertly -> i2c_al is asserted after 2 clks . Why is that ? (according to spec core suppose to work also in high speed) 2. Is there a way that i can change setup and hold time of master? thank you, omer _______________________________________________ http://www.opencores.org/mailman/listinfo/cores _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

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