I am working on a customized processor for specific application in my thesis. my application is described on ANSI C and I can compile it with any gcc based compiler, by the way I want just compare the performance of my processor with a other general purpose processor core and report it. are there any public tool which can compile my application on emulated processor core like MIPS and tell me how many clock cycles needed for execution ? please let me know if you need more information. -- Best regards, Alireza Haghdoost -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20080808/7f7d7f6f/attachment.htm

Hi, Have you written your CPU in HDL or is it somekind of emulator in C? Do you have a C compiler for it? if so the following would work good: The zpu project contains a good C source for the dhrystone benchmark. You will have to do some minor changes in it: - Implement the readMicroseconds() function, a timer that can count microseconds (a counter in your HDL code) - You need to implement an outbyte function that writes characters to the "screen" Then you could run the whole thing in modelsim or on a board (your "screen" can be a UART then). This is also a good bugtest, I tested my MIPS cpu this way. (btw, if your cpu is written in C maybe you could the same thing as long as the readMicroseconds counts "your-cpu-time" and not OS time) // Carl 2008/8/8 Alireza Haghdoost haghdoost at gmail.com>:

On Fri, 2008-08-08 at 08:31 +0430, Alireza Haghdoost wrote:
Hi Alireza, You can get the data for the OpenRISC 1000 architecture using either the architectural simulator, Or1ksim for approximate cycle information, or compiling the Verilog with Verilator (http://www.veripool.org/wiki/verilator) for cycle accurate information. Fabrice Bellard supports a range of architectures with his QEMU emulator (http://bellard.org/qemu/). However remember that these are NOT cycle accurate. You could try compiling the OpenSPARC with Verilator to get a cycle accurate model of a SPARC architecture. Other SPARC alternatives include SimplyRISC (http://www.srisc.com and on OpenCores) and the LEON processor from Gaisler Research (http://www.gaisler.com/cms/ ), although the latter is in VHDL. You also need to specify your memory architecture - that will hugely impact clock cycles when you run your code. Try running your code on OpenRISC with relatively slow memory and then disabling the caches to see the effect! HTH, Jeremy Tel: +44 (1202) 416955 Cell: +44 (7970) 676050 SkypeID: jeremybennett Email: jeremy.bennett at embecosm.com Web: www.embecosm.com

Dear Jeremy Thanks for your reply, first I should appreciate you and your colleagues in Embecosm http://www.embecosm.com/> for your excellence in TLM2 OpenRISC ISS warper. as I understood about Or1ksim, for cycle accurate analysis, first I should compile my application from ANSI C to OpenRisc assembly then I could simulate it using Or1ksim. Did you hear about MIPS SDE lite ? can I do same analysis using this tool on the MIPS cores ? Regards Alireza Haghdoost On Fri, Aug 8, 2008 at 11:45 AM, Jeremy Bennett jeremy.bennett at embecosm.com

-- Best regards, Alireza Haghdoost -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20080808/e7508127/attachment-0001.htm

On Fri, 2008-08-08 at 19:12 +0430, Alireza Haghdoost wrote:
Hi Alireza, You can use this approach with any processor model for which you have the tool chain. You can use the Verilator approach with any processor for which you have the Verilog code. I'm not familiar with SDE Lite, but there are a lot of MIPS cores around, some free, some not. The very early MIPS cores I believe are out of patent (the first RISC papers on which this is based came out 1980-82). Beware that all architectural simulators are only cycle *approximate*. They will have simple models of memory latency etc. My professional experience is that with a pipelined processor they can be out by a factor of 3. Ignore the marketing staff for modeling companies who tell you about +/- 10%. That's only for some very well behaved straightline application code. There are various free (cycle approximate) simulators included with GDB. They are used to test the debugger and can also be run standalone. In general free simulators will be slow (in the 1-2 MIPS range). Modern JIT compiling ISS run at 200MHz+, (ARM SystemGenerator, ARC Turbo-xISS etc), but cost $5k/seat. I have heard that QEMU (free) is fast, but I have not measured it myself. If you want cycle counts that are meaningful you will either have to use a simulator on the Verilog (various commercial ones and some free ones like IcarusVerilog) or for higher performance use a tool to convert the Verilog automatically to cycle accurate C (various commercial tools, Verilator is free). This will also require you to explicitly model the memory sub-system. Your results will be different depending on the speed of the memory you use. HTH, Jeremy -- Tel: +44 (1202) 416955 Cell: +44 (7970) 676050 SkypeID: jeremybennett Email: jeremy.bennett at embecosm.com Web: www.embecosm.com