Hi friends, Now.... as a beginner.... When i write a code for ex. counter, shift register, CLAdder, MUX.. etc(basic combo + Seq. Ckt)... With discussion on constraints i came to know that constraints are given by RTL person. RTL designers know that constraints on the. input values in their design Now, for such kind of desings stated above, how can i specify constraints to synthesis person.....constrai nts like.... 1) Timing Constriants 2) set input delay on input signals... & output delay on outputs 3) Set load on inputs & outputs 4) Clock latency. And so on.... For such kind of simple examples how can i give constraints( above mentioned) to the synthesis person. I've some forcastation let me state that.... 1) We are writing RTL independent of tech library, and not knowing delays involved. If this is the case, how come RTL desinger tell constraints regarding DELAY. 2) Is it required that RTL desinger should know Tech. Library information, to give the constraints.... 3) What Architect plays role in defining constraints. . I'll be really greatfully if we have discussion for the above stated matters.... Thanks TaRa -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20080827/c9eb6bb6/attachment.html