I am an FPGA newb but have some experience with sequential logic design in VHDL for CPLDs including things like UARTS, SPI peripherals etc   Can anyone give me an idea of the volume of work required to create a functional Waverfront AL3101 core (without the peak metering unit) in a Xilnx Spartan FPGA ? (www.wavefrontsemi.com)   I am aware that it is not a MAC or memory efficient way of doing DSP on an FPGA and not something you would normally want to do, but the tradeoff is that it seems to be an architecture that would be quite easy to implement.   Any pointers? -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20080906/b41ed456/attachment-0001.htm