So would I .

We have known for decades that the only way that this industry will
survive is for us to reuse our designs and not have to reinvent( and
redocument and reverify) the wheel every time we do a chip design.

But we still do not have a industry wide process for taking a design
proven in one target process and porting it to another. We must
manually deconstruct the ip and then rebuild it for a different target.

Opencores is a design for reuse website. We should have a document
that tells designers how to make sure that their IP will easily port
to other target processes.

Every attempt by the EDA industry to do this has failed simply because
the industry tries to create something that so complex that it
requires the purchase of an expensive tool in order to use it.

We are not under that constraint. This is a perfect open source
project. Collect the wisdom of opencores community on how to make ip
portable and demonstrate it by using the techniques on opencores projects.

Most of the problems I see in reuse are due to the designer simply not
realizing that somethings that are ok for a local project will cause
problems if you want to retarget the design.

We need to create a document that tells designers what to do or not do
in their ip.

I am willing to add my input and work on this. Do we have enough
support to reach
critical mass?

John Eaton

And my two penny worth Shall we start a list ? Top of list, Include documentation on the interface. Keep doc simple. After that, we get tool specific, which leads to problems, but something is better than nothing. Include a test bench that is stand alone ( include a build script that works from 'blank' ) Include a build script for a synth tool. I mainly do VHDL, but if I have the above even Verilog and different tools are much easier. Andrew -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of z3qmtr45 at iinet.com Sent: 20 September 2008 05:46 To: cores at opencores.org Subject: [oc] Design for Reuse So would I . We have known for decades that the only way that this industry will survive is for us to reuse our designs and not have to reinvent( and redocument and reverify) the wheel every time we do a chip design. But we still do not have a industry wide process for taking a design proven in one target process and porting it to another. We must manually deconstruct the ip and then rebuild it for a different target. Opencores is a design for reuse website. We should have a document that tells designers how to make sure that their IP will easily port to other target processes. Every attempt by the EDA industry to do this has failed simply because the industry tries to create something that so complex that it requires the purchase of an expensive tool in order to use it. We are not under that constraint. This is a perfect open source project. Collect the wisdom of opencores community on how to make ip portable and demonstrate it by using the techniques on opencores projects. Most of the problems I see in reuse are due to the designer simply not realizing that somethings that are ok for a local project will cause problems if you want to retarget the design. We need to create a document that tells designers what to do or not do in their ip. I am willing to add my input and work on this. Do we have enough support to reach critical mass? John Eaton _______________________________________________ http://www.opencores.org/mailman/listinfo/cores No virus found in this incoming message. Checked by AVG - http://www.avg.com Version: 8.0.138 / Virus Database: 270.7.0/1682 - Release Date: 20/09/2008 10:24

----- Original Message ----- From: andrew mulcockspam at m...> To: Date: Sat Sep 20 21:08:30 CEST 2008 Subject: [oc] Design for Reuse

Thats interfaces. Every signal passed between components in a SOC must
do so via a defined interface. The definition includes:

1) Interface name
2) Ports and signals
3) Protocol
4) Identify clocks,resets and clock enables
5) list reset state for all signals
6) Synthesis and timing constraints
7) A protocol checker that runs during simulations





The problem is that everybody uses different tools. I would start by
creating a list of free tools that anyone can access. Start with
icarus verilog ( is there a good free vhdl simulator) and something
like xilinx's webpack. Every component we do must be verified in
silicon. They should include test suite, synthesis scripts and a
complete design that can be loaded onto a readily available target board,




Design today consists of creating a bunch of rtl and a bunch of
scripts that when run produces a silicon ready netlist. You run one
big make and out pops a netlist.

I am interested in how you create your database so that one component
can be reused in many different chips will little extra effort. Most
of the designs that I have seen in opencores simply through everything
into one subdirectory. Thats fine for a small project but doesn't work
well for reuse.


John Eaton