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a VHDL 16550 UART core & Wishbone LPC Host and Peripheral Bridge by Thomas on Sep 30, 2008			Thomas Posts: 2 Joined: Aug 12, 2008 Last seen: Apr 10, 2026
Hi! I have a problem when implementing the 16550 UART together with the wb to lpc peripheral (using gh_vhdl_lib). I use a Endura TP945 board as a host and implement the design on a xilinx starter board. The problem is that when I try to read from the MSR register the data is wrong and the other registers is resetted. If the register is set to a constant value, everything works fine. If, for example (for bit 0 in the MSR register) the value in to the jkff is set to a constant '0', everything works fine. But otherwise, the iDCTS goes high during a read, indicating that the value on CTSn has changed (CTSn is set to '1'). This is not really a big problem since the register is not used, but I would really like to understand this. I have also tried to implement extra wait states without result. Best regards/ Thomas Hi! I have a problem when implementing the 16550 UART together with the wb to lpc peripheral (using gh_vhdl_lib). I use a Endura TP945 board as a host and implement the design on a xilinx starter board. The problem is that when I try to read from the MSR register the data is wrong and the other registers is resetted. If the register is set to a constant value, everything works fine. If, for example (for bit 0 in the MSR register) the value in to the jkff is set to a constant '0', everything works fine. But otherwise, the iDCTS goes high during a read, indicating that the value on CTSn has changed (CTSn is set to '1'). This is not really a big problem since the register is not used, but I would really like to understand this. I have also tried to implement extra wait states without result. Best regards/ Thomas

a VHDL 16550 UART core & Wishbone LPC Host and Peripheral Bridge by Unknown on Oct 1, 2008			Not available!
<A HREF="http://www.opencores.org/mailman/listinfo/cores">Thomas at opencores.org</A> wrote: [q] Hi! I have a problem when implementing the 16550 UART together with the wb to lpc peripheral (using gh_vhdl_lib). I use a Endura TP945 board as a host and implement the design on a xilinx starter board. The problem is that when I try to read from the MSR register the data is wrong and the other registers is resetted. If the register is set to a constant value, everything works fine. If, for example (for bit 0 in the MSR register) the value in to the jkff is set to a constant '0', everything works fine. But otherwise, the iDCTS goes high during a read, indicating that the value on CTSn has changed (CTSn is set to '1'). This is not really a big problem since the register is not used, but I would really like to understand this. I have also tried to implement extra wait states without result. [/q] I have found several problems in that core, but I didn't notice the issues you have. You can get my fixed version here: svn co <A HREF="http://gnuradio.org/svn/gnuradio/trunk/usrp2/fpga/opencores/uart16550">http://gnuradio.org/svn/gnuradio/trunk/usrp2/fpga/opencores/uart16550</A> Among the bugs are problems with the FIFOs and a bad wishbone interface. Matt Thomas at opencores.org wrote: Hi! I have a problem when implementing the 16550 UART together with the wb to lpc peripheral (using gh_vhdl_lib). I use a Endura TP945 board as a host and implement the design on a xilinx starter board. The problem is that when I try to read from the MSR register the data is wrong and the other registers is resetted. If the register is set to a constant value, everything works fine. If, for example (for bit 0 in the MSR register) the value in to the jkff is set to a constant '0', everything works fine. But otherwise, the iDCTS goes high during a read, indicating that the value on CTSn has changed (CTSn is set to '1'). This is not really a big problem since the register is not used, but I would really like to understand this. I have also tried to implement extra wait states without result. I have found several problems in that core, but I didn't notice the issues you have. You can get my fixed version here: svn co http://gnuradio.org/svn/gnuradio/trunk/usrp2/fpga/opencores/uart16550 Among the bugs are problems with the FIFOs and a bad wishbone interface. Matt

a VHDL 16550 UART core & Wishbone LPC Host and Peripheral Bridge by peio on Oct 2, 2008			peio Posts: 19 Joined: Nov 25, 2004 Last seen: Jan 14, 2026
Hi Matt, I use the a_VHDL_16550_UART core with the PCI32TLITE core to create a PCI UART Peripheral and it works very well. It runs with the Linux serial driver without problems. Probably your bug will be in other region of your project. Regards, Peio ----- Original Message ----- From: Matt Ettus<<A HREF="http://www.opencores.org/mailman/listinfo/cores">matt at e...</A>> To: Date: Wed Oct 1 08:14:02 CEST 2008 Subject: [oc] a VHDL 16550 UART core & Wishbone LPC Host and Peripheral Bridge [q] Thomas at opencores.org wrote: [q]> Hi! > > I have a problem when implementing the 16550 UART together [/q] with the wb [q]> to lpc peripheral (using gh_vhdl_lib). I use a Endura TP945 [/q] board as a [q]> host and implement the design on a xilinx starter board. The [/q] problem [q]> is that when I try to read from the MSR register the data is [/q] wrong and [q]> the other registers is resetted. If the register is set to a [/q] constant [q]> value, everything works fine. If, for example (for bit 0 in [/q] the MSR [q]> register) the value in to the jkff is set to a constant '0', > everything works fine. But otherwise, the iDCTS goes high [/q] during a [q]> read, indicating that the value on CTSn has changed (CTSn is [/q] set to '1'). [q]> This is not really a big problem since the register is not [/q] used, but I [q]> would really like to understand this. > I have also tried to implement extra wait states without [/q] result. [q]> [/q] I have found several problems in that core, but I didn't notice the issues you have. You can get my fixed version here: svn co <A HREF="http://gnuradio.org/svn/gnuradio/trunk/usrp2/fpga/opencores/uart16550">http://gnuradio.org/svn/gnuradio/trunk/usrp2/fpga/opencores/uart16550</A> Among the bugs are problems with the FIFOs and a bad wishbone interface. Matt [/q] Hi Matt, I use the a_VHDL_16550_UART core with the PCI32TLITE core to create a PCI UART Peripheral and it works very well. It runs with the Linux serial driver without problems. Probably your bug will be in other region of your project. Regards, Peio ----- Original Message ----- From: Matt Ettusmatt at e...> To: Date: Wed Oct 1 08:14:02 CEST 2008 Subject: [oc] a VHDL 16550 UART core & Wishbone LPC Host and Peripheral Bridge Thomas at opencores.org wrote: > Hi! > > I have a problem when implementing the 16550 UART together with the wb > to lpc peripheral (using gh_vhdl_lib). I use a Endura TP945 board as a > host and implement the design on a xilinx starter board. The problem > is that when I try to read from the MSR register the data is wrong and > the other registers is resetted. If the register is set to a constant > value, everything works fine. If, for example (for bit 0 in the MSR > register) the value in to the jkff is set to a constant '0', > everything works fine. But otherwise, the iDCTS goes high during a > read, indicating that the value on CTSn has changed (CTSn is set to '1'). > This is not really a big problem since the register is not used, but I > would really like to understand this. > I have also tried to implement extra wait states without result. > I have found several problems in that core, but I didn't notice the issues you have. You can get my fixed version here: svn co http://gnuradio.org/svn/gnuradio/trunk/usrp2/fpga/opencores/uart16550 Among the bugs are problems with the FIFOs and a bad wishbone interface. Matt

a VHDL 16550 UART core & Wishbone LPC Host and Peripheral Bridge by Thomas on Oct 2, 2008			Thomas Posts: 2 Joined: Aug 12, 2008 Last seen: Apr 10, 2026
Hi, Thank you Matt, i will check that out! Peio, I have also used the UART core with the PCI32LITE core successfully and I also used it successfully together with an EBI to wishbone interface. I'm doing a master thesis on serial transmission using FPGAs where I am using some of the cores here, and it is very useful with your help on these issues! Regards, Thomas ----- Original Message ----- From: peio at opencores.com<<A HREF="http://www.opencores.org/mailman/listinfo/cores">peio at o...</A>> To: Date: Thu Oct 2 08:18:28 CEST 2008 Subject: [oc] a VHDL 16550 UART core & Wishbone LPC Host and Peripheral Bridge [q] Hi Matt, I use the a_VHDL_16550_UART core with the PCI32TLITE core to create a PCI UART Peripheral and it works very well. It runs with the Linux serial driver without problems. Probably your bug will be in other region of your project. Regards, Peio ----- Original Message ----- From: Matt Ettus<matt at e...> To: Date: Wed Oct 1 08:14:02 CEST 2008 Subject: [oc] a VHDL 16550 UART core & Wishbone LPC Host and Peripheral Bridge [q]> Thomas at opencores.org wrote: [q] > Hi! > > I have a problem when implementing the 16550 UART [/q] together [q]> with the wb [q] > to lpc peripheral (using gh_vhdl_lib). I use a Endura [/q] TP945 [q]> board as a [q] > host and implement the design on a xilinx starter board. [/q] The [q]> problem [q] > is that when I try to read from the MSR register the data [/q] is [q]> wrong and [q] > the other registers is resetted. If the register is set [/q] to a [q]> constant [q] > value, everything works fine. If, for example (for bit 0 [/q] in [q]> the MSR [q] > register) the value in to the jkff is set to a constant [/q] '0', [q] > everything works fine. But otherwise, the iDCTS goes high [/q] > during a [q] > read, indicating that the value on CTSn has changed (CTSn [/q] is [q]> set to '1'). [q] > This is not really a big problem since the register is [/q] not [q]> used, but I [q] > would really like to understand this. > I have also tried to implement extra wait states without [/q] > result. [q] > [/q] > I have found several problems in that core, but I didn't [/q] notice the [q]> issues you have. You can get my fixed version here: > svn co > > [/q] <A HREF="http://gnuradio.org/svn/gnuradio/trunk/usrp2/fpga/opencores/uart16550">http://gnuradio.org/svn/gnuradio/trunk/usrp2/fpga/opencores/uart16550</A> [q]> Among the bugs are problems with the FIFOs and a bad wishbone > interface. > Matt > > [/q] [/q] Hi, Thank you Matt, i will check that out! Peio, I have also used the UART core with the PCI32LITE core successfully and I also used it successfully together with an EBI to wishbone interface. I'm doing a master thesis on serial transmission using FPGAs where I am using some of the cores here, and it is very useful with your help on these issues! Regards, Thomas ----- Original Message ----- From: peio at opencores.compeio at o...> To: Date: Thu Oct 2 08:18:28 CEST 2008 Subject: [oc] a VHDL 16550 UART core & Wishbone LPC Host and Peripheral Bridge Hi Matt, I use the a_VHDL_16550_UART core with the PCI32TLITE core to create a PCI UART Peripheral and it works very well. It runs with the Linux serial driver without problems. Probably your bug will be in other region of your project. Regards, Peio ----- Original Message ----- From: Matt Ettus To: Date: Wed Oct 1 08:14:02 CEST 2008 Subject: [oc] a VHDL 16550 UART core & Wishbone LPC Host and Peripheral Bridge > Thomas at opencores.org wrote: > Hi! > > I have a problem when implementing the 16550 UART together > with the wb > to lpc peripheral (using gh_vhdl_lib). I use a Endura TP945 > board as a > host and implement the design on a xilinx starter board. The > problem > is that when I try to read from the MSR register the data is > wrong and > the other registers is resetted. If the register is set to a > constant > value, everything works fine. If, for example (for bit 0 in > the MSR > register) the value in to the jkff is set to a constant '0', > everything works fine. But otherwise, the iDCTS goes high > during a > read, indicating that the value on CTSn has changed (CTSn is > set to '1'). > This is not really a big problem since the register is not > used, but I > would really like to understand this. > I have also tried to implement extra wait states without > result. > > I have found several problems in that core, but I didn't notice the > issues you have. You can get my fixed version here: > svn co > > http://gnuradio.org/svn/gnuradio/trunk/usrp2/fpga/opencores/uart16550 > Among the bugs are problems with the FIFOs and a bad wishbone > interface. > Matt > >

a VHDL 16550 UART core & Wishbone LPC Host and Peripheral Bridge by Unknown on Oct 2, 2008			Not available!
<A HREF="http://www.opencores.org/mailman/listinfo/cores">Thomas at opencores.org</A> wrote: [q] Hi, Thank you Matt, i will check that out! Peio, I have also used the UART core with the PCI32LITE core successfully and I also used it successfully together with an EBI to wishbone interface. I'm doing a master thesis on serial transmission using FPGAs where I am using some of the cores here, and it is very useful with your help on these issues! [/q] Actually, the bugs I found are in the verilog 16550 core, not the vhdl one. I have not used the vhdl core. Matt Thomas at opencores.org wrote: Hi, Thank you Matt, i will check that out! Peio, I have also used the UART core with the PCI32LITE core successfully and I also used it successfully together with an EBI to wishbone interface. I'm doing a master thesis on serial transmission using FPGAs where I am using some of the cores here, and it is very useful with your help on these issues! Actually, the bugs I found are in the verilog 16550 core, not the vhdl one. I have not used the vhdl core. Matt

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