Hallo,
I'm not sure I found a bug but I used the core and I found a problem.
I'm using 9600 baudrate with fifo trigger level set to 1 and no dma.
Transmission goes perfectly but reception has the following strange
behaviour: if I send to the UART the letter A, it receives another
character (0). If, after letter A I send the letter B, it still receives 0.
Only after 15 transmissions of characters, the UART actually receives
letter A, and following another transmission of a character, it receives
the letter B and so on.
It seems that there is a delay of 15 characters that I can't remove.
I've tried to reset the FIFO during initialization of the UART and tried to
flush it but without any result. Can anyone help me?

Thank you
Valentina

Hello valentina; I have had the same problem with the UART 16550 core. I am using this uart without the wrappers given,115200 baudrate with fifo trigger level set to 1 and no dma. I have also tried to reset it in initialization with no luck. Also tried to flush it (reading 15 times in it during initialization), but the same. I thought it was a problem with the read pointer in the reception fifo, it seems as it goes one position ahead the write pointer so it need to go all over the fifo to see the received char in the next round, but cannot see the problem with the Read address counter enable (add_RD_CE)!!! I finally change the reception fifo with one from the GH_VHDL Library from the same author (gh_fifo_async_usrf.vhd) and add this signal initializated to '0' : signal iRD : STD_LOGIC:='0'; and change this original text: -------------------- process (clk_RD) begin if (rising_edge(clk_RD)) then Q valentina.lomi at i...> To: Date: Thu Nov 6 09:33:37 CET 2008 Subject: [oc] problems with UART 16550 core