Good afternoon,

I'm using the raggedstone PCI target core with a Raggedstone MINI-CAN board.
(Xilinx Spartan-3 1500). It's a speed grade -4 device, and I'm just trying
to build the 7seg circuit (I know I don't have the hardware on the card, but
the PCI interface is the same).

It builds (and in fact I've build a little TDM preknown-data-generator on this
board) but whenever I build the system I get a constraint warning, saying
that it can't meet my PCI bus timing of "OUT 11 ns AFTER COMP "PCLK"".

It's close (14.3ns) but shouldn't this be achievable? I've switched to timing
based layout, upped my number of iterations to 5, as suggested by the par
utility, but still no go.

Now, this board also has a 32MHz oscillator on it, and if I uncomment the
constraints for that, I get constraint errors as well. I'm sure it's
something really simple, but so far I've not been able to figure it out.

If it isn't apparent, I am quite an FPGA newbie.

-A.