Hello, Everybody, I would like to test the wishbone_bfm example. If i test the code as is and run the simulation, i can see that nothing happens on the wb bus ( http://www.shrani.si/?c/Cz/4Df1QXLZ/1.jpg ). If i comment out the wb_init and wb_rst command ( http://www.shrani.si/?W/26/2F7oodTX/3.jpg ) the first data transfer of bkw_32 is done, and than again nothing else happens ( http://www.shrani.si/?36/7p/2cOB8VAK/2.jpg ). Why is that? Regards Klemen

Let me answer to myself :)

The problem was in ISE simulator. It seems that it doesn't work as suppose to. After i installed ModelSim, everything worked fine.

Regards
Klemen

well done ---- Klemen Dovrtel klemen_dovrtel at yahoo.com> wrote:

Let me answer to myself :)

The problem was in ISE simulator. It seems that it doesn't work as suppose to. After i installed ModelSim, everything worked fine.

Regards
Klemen



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I have one more question about wb_bfm: It is written in wishbone specifications that "All WISHBONE output signals are registered at the rising edge of [CLK_I]. All WISHBONE input signals are stable before the rising edge of [CLK_I]". This can be also seen on wishbone timing diagrams ( http://www.shrani.si/f/3x/ao/169SY1Ep/wb1.jpg ). Now if you look at wb_bfm example simulation ( http://www.shrani.si/f/b/ra/2OvBoP0Y/wbbfm.jpg ), you can see that all wishbone signals change its state exactly at rising edge of clock cycle. Isn't this contrary to what is written wishbone specifications? Regards Klemen
doesn't work as suppose to. After i installed ModelSim,
everything worked fine.

You are confusing real world and simulation environments. What you see on your simulator is not what would happen in silicon. Most notably for RTL simulations there is (usually) no timing information. Hence all signals transition directly at/after the clock edge. Richard -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of Klemen Dovrtel Sent: 13 December 2008 17:59 To: Discussion list about free open source IP cores; andrew.mulcock.gg at ntlworld.com Subject: Re: [oc] wishbone_bfm example I have one more question about wb_bfm: It is written in wishbone specifications that "All WISHBONE output signals are registered at the rising edge of [CLK_I]. All WISHBONE input signals are stable before the rising edge of [CLK_I]". This can be also seen on wishbone timing diagrams ( http://www.shrani.si/f/3x/ao/169SY1Ep/wb1.jpg ). Now if you look at wb_bfm example simulation ( http://www.shrani.si/f/b/ra/2OvBoP0Y/wbbfm.jpg ), you can see that all wishbone signals change its state exactly at rising edge of clock cycle. Isn't this contrary to what is written wishbone specifications? Regards Klemen
doesn't work as suppose to. After i installed ModelSim,
everything worked fine.
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