Hello everybody

im a student at a University in Germany and im trying to implement the
I2C controller core, i am not that experienced in VHDL but im doing my
best. I would appreciate if you could answer my questions.

my questions are:

1) im using the simple i2c and ts_ds1621 that is provided with the core.
This simple core should complete, so if i synthesize it and load it onto
my Basys board i should get some activity at the sda and scl lines, right?
But i am not getting any activity at all, for your information: i used a
clock divider (the core is driven by 1Hz) and send copies of the sda and
scl signals to the leds, to see whats going on (i could send you a copy
of the code if its unclear what i mean). Is there anything else i have to
do to get some acivity, cause i think i should see some activity even if
theres no ds1621 on the bus (especially at that low clock rate).
Do i need some kind of start signal to get it to work? Does the bus have
to be pulled up externally or is it enough to define it as pullup in the
user constraints file?

2) if im using the wb i2c controller core the doc says i have to add the
tri-state buffers at a higher hierarchical level. So do i have to make a
new toplevel entity that uses the original master top as component and
instantiates it, then insert these buffer there? Then i think i would have
to use some kind of Wishbone master that sends the wishbone signals
to the controller, cause i just wanna use the controller to read/write
from/to i2c devices and show the data on 7 segment leds (for now).
The wishbone part is perhaps the one i struggle, i know its great when u
combine different cores, but when you just want to use the i2c
controller its a bit too much, escpecially if your not that experienced to
the cores and wishbone, but thats just my opinion, im sure i will change
my mind later if i understand the whole concept.
could anybody perhaps give me a small example in vhdl how to make a
wishbone master to read/write from a i2c device or is that in the
wishbone documentation ( if so i must have missed sth and have to look
through it again).

best regards
Thomas Roesler

Hi Thomas, Do you need to use VHDL? Because if you use Verilog I might be able to help Regards Lai -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of Thomas.Roesler at hs-furtwangen.de Sent: Thursday, December 11, 2008 12:04 AM To: cores at opencores.org Subject: [oc] I2C controller core Hello everybody im a student at a University in Germany and im trying to implement the I2C controller core, i am not that experienced in VHDL but im doing my best. I would appreciate if you could answer my questions. my questions are: 1) im using the simple i2c and ts_ds1621 that is provided with the core. This simple core should complete, so if i synthesize it and load it onto my Basys board i should get some activity at the sda and scl lines, right? But i am not getting any activity at all, for your information: i used a clock divider (the core is driven by 1Hz) and send copies of the sda and scl signals to the leds, to see whats going on (i could send you a copy of the code if its unclear what i mean). Is there anything else i have to do to get some acivity, cause i think i should see some activity even if theres no ds1621 on the bus (especially at that low clock rate). Do i need some kind of start signal to get it to work? Does the bus have to be pulled up externally or is it enough to define it as pullup in the user constraints file? 2) if im using the wb i2c controller core the doc says i have to add the tri-state buffers at a higher hierarchical level. So do i have to make a new toplevel entity that uses the original master top as component and instantiates it, then insert these buffer there? Then i think i would have to use some kind of Wishbone master that sends the wishbone signals to the controller, cause i just wanna use the controller to read/write from/to i2c devices and show the data on 7 segment leds (for now). The wishbone part is perhaps the one i struggle, i know its great when u combine different cores, but when you just want to use the i2c controller its a bit too much, escpecially if your not that experienced to the cores and wishbone, but thats just my opinion, im sure i will change my mind later if i understand the whole concept. could anybody perhaps give me a small example in vhdl how to make a wishbone master to read/write from a i2c device or is that in the wishbone documentation ( if so i must have missed sth and have to look through it again). best regards Thomas Roesler _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

Some quick answers... #1 I recommend you use external pull-up resistors. Although the on-chip pull-up might work as well. If you don't initiate a transfer you don't see any activity; the SCL and SDA lines should just remain high. #2 The tri-state buffers are required. You have to add these at a higher level (outside of the IP core). The core is a wishbone slave device, which means you must use an external master that configures the i2c IP and sends commands to it. Out of the box the i2c IP does not do anything; it only responds to commands from the master. Richard -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of Thomas.Roesler at hs-furtwangen.de Sent: 10 December 2008 17:04 To: cores at opencores.org Subject: [oc] I2C controller core Hello everybody im a student at a University in Germany and im trying to implement the I2C controller core, i am not that experienced in VHDL but im doing my best. I would appreciate if you could answer my questions. my questions are: 1) im using the simple i2c and ts_ds1621 that is provided with the core. This simple core should complete, so if i synthesize it and load it onto my Basys board i should get some activity at the sda and scl lines, right? But i am not getting any activity at all, for your information: i used a clock divider (the core is driven by 1Hz) and send copies of the sda and scl signals to the leds, to see whats going on (i could send you a copy of the code if its unclear what i mean). Is there anything else i have to do to get some acivity, cause i think i should see some activity even if theres no ds1621 on the bus (especially at that low clock rate). Do i need some kind of start signal to get it to work? Does the bus have to be pulled up externally or is it enough to define it as pullup in the user constraints file? 2) if im using the wb i2c controller core the doc says i have to add the tri-state buffers at a higher hierarchical level. So do i have to make a new toplevel entity that uses the original master top as component and instantiates it, then insert these buffer there? Then i think i would have to use some kind of Wishbone master that sends the wishbone signals to the controller, cause i just wanna use the controller to read/write from/to i2c devices and show the data on 7 segment leds (for now). The wishbone part is perhaps the one i struggle, i know its great when u combine different cores, but when you just want to use the i2c controller its a bit too much, escpecially if your not that experienced to the cores and wishbone, but thats just my opinion, im sure i will change my mind later if i understand the whole concept. could anybody perhaps give me a small example in vhdl how to make a wishbone master to read/write from a i2c device or is that in the wishbone documentation ( if so i must have missed sth and have to look through it again). best regards Thomas Roesler _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

hello thanks to your answers so far. to Lai, Soon Chong: im afraid i have to use vhdl cause we only learn vhdl here and the code might be used later by other students. to Richard Herveille: #1: i tried both actually but i think external pull-ups should be better (just a feeling). And yes you are right i only get a constant high on SDA and SCL. so how do i initate a transfer with the simple i2c core? i thought that with the tst_ds1621 ( the dallas statemachine) i would get some activity since theres no other input, other than clock and reset. #2 so if i use something like the following toplevel on top of the i2c_master_top, and some wishbone master on top of the i2c_controller_toplevel the more complex i2c controller works? (the wishbone master would then be a statemachine that reads or writes from/to the wishbone bus) --code on top of i2c_master_top (the same from the avalon interface posted before) entity i2c_controller_toplevel is port ( -- signals from wishbone interface (arst_i was removed) wb_clk_i : in std_logic; -- master clock input wb_rst_i : in std_logic := '0'; -- synchronous active high reset wb_adr_i : in std_logic_vector(2 downto 0); - - lower address bits wb_dat_i : in std_logic_vector(7 downto 0); -- Databus input wb_dat_o : out std_logic_vector(7 downto 0); -- Databus output wb_we_i : in std_logic; -- Write enable input wb_stb_i : in std_logic; -- Strobe signals / core select signal wb_cyc_i : in std_logic; -- Valid bus cycle input wb_ack_o : out std_logic; -- Bus cycle acknowledge output wb_inta_o : out std_logic; -- interrupt request output signal -- I2C singals: SCL and SDA scl : inout std_logic; sda : inout std_logic ); end entity; architecture structural of i2c_controller_toplevel is -- whishbone toplevel component component i2c_master_top is generic( ARST_LVL : std_logic := '0' -- asynchronous reset level ); port ( -- wishbone signals wb_clk_i : in std_logic; -- master clock input wb_rst_i : in std_logic := '0'; -- synchronous active high reset arst_i : in std_logic := not ARST_LVL; -- asynchronous reset wb_adr_i : in unsigned(2 downto 0); -- lower address bits wb_dat_i : in std_logic_vector(7 downto 0); -- Databus input wb_dat_o : out std_logic_vector(7 downto 0); -- Databus output wb_we_i : in std_logic; -- Write enable input wb_stb_i : in std_logic; -- Strobe signals / core select signal wb_cyc_i : in std_logic; -- Valid bus cycle input wb_ack_o : out std_logic; -- Bus cycle acknowledge output wb_inta_o : out std_logic; -- interrupt request output signal -- i2c lines scl_pad_i : in std_logic; -- i2c clock line input scl_pad_o : out std_logic; -- i2c clock line output scl_padoen_o : out std_logic; -- i2c clock line output enable, active low sda_pad_i : in std_logic; -- i2c data line input sda_pad_o : out std_logic; -- i2c data line output sda_padoen_o : out std_logic -- i2c data line output enable, active low ); end component i2c_master_top; -- signals for i2c lines signal scl_pad_i : std_logic; -- i2c clock line input signal scl_pad_o : std_logic; -- i2c clock line output signal scl_padoen_o : std_logic; -- i2c clock line output enable, active low signal sda_pad_i : std_logic; -- i2c data line input signal sda_pad_o : std_logic; -- i2c data line output signal sda_padoen_o : std_logic; -- i2c data line output enable, active low begin -- instantiate I2C master I2C_WB : i2c_master_top generic map ( ARST_LVL => '0' -- set async reset level to 0 ) port map( wb_clk_i, wb_rst_i, '1', -- note: ARST_LVL is set to 0 in generic map unsigned(wb_adr_i), wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o, -- i2c lines scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o ); -- tri-state buffer creation scl richard at h...> To: Date: Thu Dec 11 13:58:41 CET 2008 Subject: [oc] I2C controller core

If you're using the tst_ds1621 then you should see some activity. Make sure the clock is running and that you correctly reset (level??) the design. Richard -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of Thomas.Roesler at hs-furtwangen.de Sent: 13 December 2008 03:04 To: cores at opencores.org Subject: Re: [oc] I2C controller core hello thanks to your answers so far. to Lai, Soon Chong: im afraid i have to use vhdl cause we only learn vhdl here and the code might be used later by other students. to Richard Herveille: #1: i tried both actually but i think external pull-ups should be better (just a feeling). And yes you are right i only get a constant high on SDA and SCL. so how do i initate a transfer with the simple i2c core? i thought that with the tst_ds1621 ( the dallas statemachine) i would get some activity since theres no other input, other than clock and reset. #2 so if i use something like the following toplevel on top of the i2c_master_top, and some wishbone master on top of the i2c_controller_toplevel the more complex i2c controller works? (the wishbone master would then be a statemachine that reads or writes from/to the wishbone bus) --code on top of i2c_master_top (the same from the avalon interface posted before) entity i2c_controller_toplevel is port ( -- signals from wishbone interface (arst_i was removed) wb_clk_i : in std_logic; -- master clock input wb_rst_i : in std_logic := '0'; -- synchronous active high reset wb_adr_i : in std_logic_vector(2 downto 0); - - lower address bits wb_dat_i : in std_logic_vector(7 downto 0); -- Databus input wb_dat_o : out std_logic_vector(7 downto 0); -- Databus output wb_we_i : in std_logic; -- Write enable input wb_stb_i : in std_logic; -- Strobe signals / core select signal wb_cyc_i : in std_logic; -- Valid bus cycle input wb_ack_o : out std_logic; -- Bus cycle acknowledge output wb_inta_o : out std_logic; -- interrupt request output signal -- I2C singals: SCL and SDA scl : inout std_logic; sda : inout std_logic ); end entity; architecture structural of i2c_controller_toplevel is -- whishbone toplevel component component i2c_master_top is generic( ARST_LVL : std_logic := '0' -- asynchronous reset level ); port ( -- wishbone signals wb_clk_i : in std_logic; -- master clock input wb_rst_i : in std_logic := '0'; -- synchronous active high reset arst_i : in std_logic := not ARST_LVL; -- asynchronous reset wb_adr_i : in unsigned(2 downto 0); -- lower address bits wb_dat_i : in std_logic_vector(7 downto 0); -- Databus input wb_dat_o : out std_logic_vector(7 downto 0); -- Databus output wb_we_i : in std_logic; -- Write enable input wb_stb_i : in std_logic; -- Strobe signals / core select signal wb_cyc_i : in std_logic; -- Valid bus cycle input wb_ack_o : out std_logic; -- Bus cycle acknowledge output wb_inta_o : out std_logic; -- interrupt request output signal -- i2c lines scl_pad_i : in std_logic; -- i2c clock line input scl_pad_o : out std_logic; -- i2c clock line output scl_padoen_o : out std_logic; -- i2c clock line output enable, active low sda_pad_i : in std_logic; -- i2c data line input sda_pad_o : out std_logic; -- i2c data line output sda_padoen_o : out std_logic -- i2c data line output enable, active low ); end component i2c_master_top; -- signals for i2c lines signal scl_pad_i : std_logic; -- i2c clock line input signal scl_pad_o : std_logic; -- i2c clock line output signal scl_padoen_o : std_logic; -- i2c clock line output enable, active low signal sda_pad_i : std_logic; -- i2c data line input signal sda_pad_o : std_logic; -- i2c data line output signal sda_padoen_o : std_logic; -- i2c data line output enable, active low begin -- instantiate I2C master I2C_WB : i2c_master_top generic map ( ARST_LVL => '0' -- set async reset level to 0 ) port map( wb_clk_i, wb_rst_i, '1', -- note: ARST_LVL is set to 0 in generic map unsigned(wb_adr_i), wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o, -- i2c lines scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o ); -- tri-state buffer creation scl richard at h...> To: Date: Thu Dec 11 13:58:41 CET 2008 Subject: [oc] I2C controller core _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

Hi Thomas, Instead of using the I2C to toggle the BUS, can you write a simple VHDL just to drive the I2S (SCL, SDA) high and low, see if you have correctly assigned the output pin and pull up are not too low? Just a debugging tips Regards Lai -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of Richard Herveille Sent: Saturday, December 13, 2008 9:52 PM To: 'Discussion list about free open source IP cores' Subject: RE: [oc] I2C controller core If you're using the tst_ds1621 then you should see some activity. Make sure the clock is running and that you correctly reset (level??) the design. Richard -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of Thomas.Roesler at hs-furtwangen.de Sent: 13 December 2008 03:04 To: cores at opencores.org Subject: Re: [oc] I2C controller core hello thanks to your answers so far. to Lai, Soon Chong: im afraid i have to use vhdl cause we only learn vhdl here and the code might be used later by other students. to Richard Herveille: #1: i tried both actually but i think external pull-ups should be better (just a feeling). And yes you are right i only get a constant high on SDA and SCL. so how do i initate a transfer with the simple i2c core? i thought that with the tst_ds1621 ( the dallas statemachine) i would get some activity since theres no other input, other than clock and reset. #2 so if i use something like the following toplevel on top of the i2c_master_top, and some wishbone master on top of the i2c_controller_toplevel the more complex i2c controller works? (the wishbone master would then be a statemachine that reads or writes from/to the wishbone bus) --code on top of i2c_master_top (the same from the avalon interface posted before) entity i2c_controller_toplevel is port ( -- signals from wishbone interface (arst_i was removed) wb_clk_i : in std_logic; -- master clock input wb_rst_i : in std_logic := '0'; -- synchronous active high reset wb_adr_i : in std_logic_vector(2 downto 0); - - lower address bits wb_dat_i : in std_logic_vector(7 downto 0); -- Databus input wb_dat_o : out std_logic_vector(7 downto 0); -- Databus output wb_we_i : in std_logic; -- Write enable input wb_stb_i : in std_logic; -- Strobe signals / core select signal wb_cyc_i : in std_logic; -- Valid bus cycle input wb_ack_o : out std_logic; -- Bus cycle acknowledge output wb_inta_o : out std_logic; -- interrupt request output signal -- I2C singals: SCL and SDA scl : inout std_logic; sda : inout std_logic ); end entity; architecture structural of i2c_controller_toplevel is -- whishbone toplevel component component i2c_master_top is generic( ARST_LVL : std_logic := '0' -- asynchronous reset level ); port ( -- wishbone signals wb_clk_i : in std_logic; -- master clock input wb_rst_i : in std_logic := '0'; -- synchronous active high reset arst_i : in std_logic := not ARST_LVL; -- asynchronous reset wb_adr_i : in unsigned(2 downto 0); -- lower address bits wb_dat_i : in std_logic_vector(7 downto 0); -- Databus input wb_dat_o : out std_logic_vector(7 downto 0); -- Databus output wb_we_i : in std_logic; -- Write enable input wb_stb_i : in std_logic; -- Strobe signals / core select signal wb_cyc_i : in std_logic; -- Valid bus cycle input wb_ack_o : out std_logic; -- Bus cycle acknowledge output wb_inta_o : out std_logic; -- interrupt request output signal -- i2c lines scl_pad_i : in std_logic; -- i2c clock line input scl_pad_o : out std_logic; -- i2c clock line output scl_padoen_o : out std_logic; -- i2c clock line output enable, active low sda_pad_i : in std_logic; -- i2c data line input sda_pad_o : out std_logic; -- i2c data line output sda_padoen_o : out std_logic -- i2c data line output enable, active low ); end component i2c_master_top; -- signals for i2c lines signal scl_pad_i : std_logic; -- i2c clock line input signal scl_pad_o : std_logic; -- i2c clock line output signal scl_padoen_o : std_logic; -- i2c clock line output enable, active low signal sda_pad_i : std_logic; -- i2c data line input signal sda_pad_o : std_logic; -- i2c data line output signal sda_padoen_o : std_logic; -- i2c data line output enable, active low begin -- instantiate I2C master I2C_WB : i2c_master_top generic map ( ARST_LVL => '0' -- set async reset level to 0 ) port map( wb_clk_i, wb_rst_i, '1', -- note: ARST_LVL is set to 0 in generic map unsigned(wb_adr_i), wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o, -- i2c lines scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o ); -- tri-state buffer creation scl richard at h...> To: Date: Thu Dec 11 13:58:41 CET 2008 Subject: [oc] I2C controller core _______________________________________________ http://www.opencores.org/mailman/listinfo/cores _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

Hello so far it works now, atleast i get some activity on SDA and SCL ^^ . Looks like the scaled down clock i used to see if i get some activity was too slow and i somehow didnt see that that the nReset is low active thats why it was permanently in the idle state. But i have one more question: the clock/speed the SCL is driven has something to do with the clk_cnt right? How do i change it to match my FPGA clock? for example i have 100MHz FPGA clock and want to use 100kHz or 400kHz at the SCL. Best Regards Thomas ----- Original Message ----- From: Lai, Soon Chongsoon.chong.lai at i...> To: Date: Mon Dec 15 01:27:20 CET 2008 Subject: [oc] I2C controller core
not

downto

downto

(7 downto 0);

Write enable input

select signal

wb_ack_o :

wb_inta_o : out

scl_pad_o :

scl_padoen_o : out

sda_pad_i

std_logic;

i2c data

i2c_master_top;

line

enable,

async

wb_rst_i, '1', --

(wb_adr_i),

wb_we_i, wb_stb_i,
wb_cyc_i,

-- i2c lines scl_pad_i,
scl_pad_o,

sda_pad_o, sda_padoen_o ); --

i

Hi.. For 100KHz SCL set prescale value as 199 for 100MHz fpga clk input... For 400KHz SCL set prescale value as 49  Cheers Swami   "As soon as the fear approaches near,attack and destroy it"                                                                                                   -Chankya --- On Tue, 12/16/08, Thomas.Roesler at hs-furtwangen.de Thomas.Roesler at hs-furtwangen.de> wrote: From: Thomas.Roesler at hs-furtwangen.de Thomas.Roesler at hs-furtwangen.de> Subject: Re: [oc] I2C controller core To: cores at opencores.org Date: Tuesday, December 16, 2008, 10:00 AM Hello so far it works now, atleast i get some activity on SDA and SCL ^^ . Looks like the scaled down clock i used to see if i get some activity was too slow and i somehow didnt see that that the nReset is low active thats why it was permanently in the idle state. But i have one more question: the clock/speed the SCL is driven has something to do with the clk_cnt right? How do i change it to match my FPGA clock? for example i have 100MHz FPGA clock and want to use 100kHz or 400kHz at the SCL. Best Regards Thomas ----- Original Message ----- From: Lai, Soon Chongsoon.chong.lai at i...> To: Date: Mon Dec 15 01:27:20 CET 2008 Subject: [oc] I2C controller core
not

downto

downto

(7 downto 0);

Write enable input

select signal

wb_ack_o :

wb_inta_o : out

scl_pad_o :

scl_padoen_o : out

sda_pad_i

std_logic;

i2c data

i2c_master_top;

line

enable,

async

wb_rst_i, '1', --

(wb_adr_i),

wb_we_i, wb_stb_i,
wb_cyc_i,

-- i2c lines scl_pad_i,
scl_pad_o,

sda_pad_o, sda_padoen_o ); --

'0') else



i
_______________________________________________ http://www.opencores.org/mailman/listinfo/cores -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20081216/0e1c120e/attachment.htm

Hello Thomas:

I think you may divide the frequency. I know two methods for that

The first is general, and it consist in create a counter/divider betwen the
clock source of your FPGA and the clock input of your IP core, in this case
I2C controller.
The number of bits of the counter:

#bits_of counter = log2(FPGA_freq./Desired_freq)

This method, if no clock gatting its desirable, minimizes the duty cycle of
the clock.

The other method its to instantiate Digital Clock Managers (DCM) primitives
(on Xilinx's devices). There is not general because, for example on Altera,
Lattice or inclusive on some Xilinx's devices DCM may not be present or not
with the same options that, for example, on Spartan3 Xilinx's devices.

I hope the above explanation had been useful on some way for you.


Regards AASL.

i somehow didnt see that that the nReset is low active thats why it was permanently in the idle state. [rih] that's what the 'n' in nReset means :p But i have one more question: the clock/speed the SCL is driven has something to do with the clk_cnt right? How do i change it to match my FPGA clock? for example i have 100MHz FPGA clock and want to use 100kHz or 400kHz at the SCL. [rih] There's a prescale register. The ratio between prescale register and system clock determines the i2c clock. See the i2c documentation. BTW everybody wants to run the i2c at 100kHz or 400kHz. If you do not need this speed than don't. There's no need to run if you can walk. It makes life easier :) Best Regards Thomas ----- Original Message ----- From: Lai, Soon Chongsoon.chong.lai at i...> To: Date: Mon Dec 15 01:27:20 CET 2008 Subject: [oc] I2C controller core
not

downto

downto

(7 downto 0);

Write enable input

select signal

wb_ack_o :

wb_inta_o : out



scl_pad_o :

scl_padoen_o : out

sda_pad_i

std_logic;

i2c data

i2c_master_top;



line

enable,

async

wb_rst_i, '1', --

(wb_adr_i),

wb_we_i, wb_stb_i,
wb_cyc_i,

-- i2c lines scl_pad_i,
scl_pad_o,

sda_pad_o, sda_padoen_o ); --

i
_______________________________________________ http://www.opencores.org/mailman/listinfo/cores