Hello Everybody, I am testing the VHDL 16550 UART core. I wrote a simple test code using wb_bfm (please see the code snippet below) which simply transmits 8 bytes of data. When i run the simulation and monitor the uart TX signal, it doesn't actually look like normal uart signal (please see the simulation output below). What is this? Regards Klemen SIMULATION: uart configuration: http://www.shrani.si/f/1F/YA/w2sIHy/0.jpg first three bytes transmitted: http://www.shrani.si/f/X/wn/3FImuVl2/1.jpg (transmits 0x03 and 0x05 at the same time and later 0x03 and 0x05 separate) second three bytes transmitted: http://www.shrani.si/f/2D/p4/3efOI1Or/2.jpg (transmits 0x33 and 0x55 at the same time and later 0x33 and 0x55 separate) CODE: wb_init( bus_c); -- initalise wishbone bus wb_rst( 2, reset_int, bus_c ); -- reset system for 2 clocks clock_wait( 2, bus_c ); bka_test_array(0) := X"0000_0003"; -- LCR bkd_test_array(0) := X"0000_0083"; -- 8 data bits, 1 start bit, set LCR(7) bkw_32( bka_test_array, bkd_test_array, 1, bus_c); clock_wait( 2, bus_c ); bka_test_array(0) := X"0000_0001"; -- DLM bkd_test_array(0) := X"0000_0000"; -- BAUD bkw_32( bka_test_array, bkd_test_array, 1, bus_c); clock_wait( 2, bus_c ); bka_test_array(0) := X"0000_0000"; -- DLL bkd_test_array(0) := X"0000_0005"; -- BAUD bkw_32( bka_test_array, bkd_test_array, 1, bus_c); clock_wait( 2, bus_c ); bka_test_array(0) := X"0000_0003"; -- LCR bkd_test_array(0) := X"0000_0003"; -- 8 data bits, 1 start bit, clear LCR(7) bkw_32( bka_test_array, bkd_test_array, 1, bus_c); clock_wait( 2, bus_c ); bka_test_array(0) := X"0000_0000"; -- Transmiter fifo bkd_test_array(0) := X"0000_0003"; -- data bkw_32( bka_test_array, bkd_test_array, 1, bus_c); clock_wait( 2, bus_c ); bka_test_array(0) := X"0000_0000"; -- Transmiter fifo bkd_test_array(0) := X"0000_0005"; -- data bkw_32( bka_test_array, bkd_test_array, 1, bus_c); clock_wait( 2, bus_c ); clock_wait( 5000, bus_c ); bka_test_array(0) := X"0000_0000"; -- Transmiter fifo bkd_test_array(0) := X"0000_0003"; -- data bkw_32( bka_test_array, bkd_test_array, 1, bus_c); clock_wait( 2, bus_c ); clock_wait( 5000, bus_c ); bka_test_array(0) := X"0000_0000"; -- Transmiter fifo bkd_test_array(0) := X"0000_0005"; -- data bkw_32( bka_test_array, bkd_test_array, 1, bus_c); clock_wait( 2, bus_c ); clock_wait( 5000, bus_c ); bka_test_array(0) := X"0000_0000"; -- Transmiter fifo bkd_test_array(0) := X"0000_0033"; -- data bkw_32( bka_test_array, bkd_test_array, 1, bus_c); clock_wait( 2, bus_c ); bka_test_array(0) := X"0000_0000"; -- Transmiter fifo bkd_test_array(0) := X"0000_0055"; -- data bkw_32( bka_test_array, bkd_test_array, 1, bus_c); clock_wait( 2, bus_c ); clock_wait( 5000, bus_c ); bka_test_array(0) := X"0000_0000"; -- Transmiter fifo bkd_test_array(0) := X"0000_0033"; -- data bkw_32( bka_test_array, bkd_test_array, 1, bus_c); clock_wait( 2, bus_c ); clock_wait( 5000, bus_c ); bka_test_array(0) := X"0000_0000"; -- Transmiter fifo bkd_test_array(0) := X"0000_0055"; -- data bkw_32( bka_test_array, bkd_test_array, 1, bus_c); clock_wait( 2, bus_c ); _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

From: Rick Collins gnuarm.2006 at arius.com> Subject: Re: [oc] VHDL 16550 UART core - strange tx signal To: klemen_dovrtel at yahoo.com, cores at opencores.org Date: Sunday, December 14, 2008, 10:45 PM I don't get it. This looks perfect to me, both 1.jpg and 2.jpg. What do you see wrong? I assume this is 8 data bits, no parity and 1 stop bit, right? What do you see wrong? Rick At 07:02 AM 12/14/2008, Klemen Dovrtel wrote:
test code

simply

and monitor the

normal uart signal
http://www.shrani.si/f/1F/YA/w2sIHy/0.jpg
0x03 and 0x05

0x33 and 0x55

clocks

LCR

data bits, 1 start bit,

DLM

BAUD

DLL

BAUD

LCR

data bits, 1 start bit,

Transmiter fifo

data

Transmiter fifo

data

Transmiter fifo

data

Transmiter fifo

data

Transmiter fifo

data

Transmiter fifo

data

Transmiter fifo

data

Transmiter fifo

data