Hi, I'm having problems undestanding how the slave interrupt controller is going to work??? I've got it attached to an Intel SCH hub which defaults to quiet mode. I don't see how the slave controller will ever initiate an interrupt whilst in this mode... serirq_mode is initialised as CONTINUOUS and found_start and found_stop will never be set if the host never drives serirq_i low... meanwhile in the main state machine: irq_changed will never be asserted since serirq_mode = continuous... state will never transition from idle because found_start is never asserted and irq_changed is never asserted... Am I missing something? Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266

Mark McDougall wrote:

OK, I think I've worked this issue out. The hub driver is supposed to switch from continuous mode to quiet mode during initialisation, which happens _way_ before the lpc slave is configured in the FPGA... so I've defaulted the slave to quiet mode... that seems to work. I've also found what I believe are two (2) bugs: (1) 2 stop bits = quiet mode, 3 = continuous. The slave is decoding this the opposite way, so it was reverting to continuous mode after the 1st transaction. (2) it should be using current_irq, which is latched when a change of state is detected, for shifting out onto the bus during an interrupt reporting transaction, rather than serirq_i, which can actually change (and was in my case) during the transaction, and can cause subsequent interrupts to be missed. Still can't get it working properly for 16550 UARTs on WinXP. :( Seems the 1st interrupt on each port is serviced, but subsequent interrupts are ignored. Currently steering IRQ 4,3... Anyone else had any luck? Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266

Mark McDougall wrote:

OK, sorted! Legacy interrupts are active high - DOH!!! Anyway, I believe the two aforementioned bugs stand. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266

Hello Mark, I fixed the stop cycle for continuous and quiet modes. I will look into the latched irq input. But keep in mind, the serirq core is not an interrupt controller, ie, it cannot handle asynchronous interrupt inputs. For testing, I used the simple_pic interrupt controller on OpenCores.org as the actual interrupt controller. I would like to know more about your project and success with the serirq core, so I can add the information to the status portion of the webpage. As I mentioned on the wb_lpc page, this has not yet (until your work) been tested with a 3rd party host/peripheral. Thanks, Howard ----- Original Message ----- From: Mark McDougallmarkm at v...> To: Date: Tue Dec 23 00:45:17 CET 2008 Subject: [oc] Wishbone LPC Host & Peripheral - interrupts?