Hello, I am fairly new to FPGA logic design in general and was hoping that I might get some guidance on how to go about writing a WISHBONE wrapper for my Xilinx Core Generator generated DDR2 SDRAM controller. Basically, I have these user interface signals to deal with (hopefully the signals are self explanatory from the naming scheme): cntrl0_burst_done cntrl0_user_command_register cntrl0_user_data_mask cntrl0_user_input_data cntrl0_user_input_address cntrl0_init_done cntrl0_ar_done cntrl0_auto_ref_req cntrl0_user_cmd_ack cntrl0_clk_tb cntrl0_clk90_tb cntrl0_sys_rst_tb cntrl0_sys_rst90_tb cntrl0_sys_rst180_tb cntrl0_user_data_valid cntrl0_user_output_data I am just confused on what to do with these signals and how to interface them to the wishbone bus. Thanks in advance for any suggestions or pointing to relevant documentation. -- Newell http://www.gempillar.com Before enlightenment: chop wood, carry water After enlightenment: code, build circuits -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20081230/c9afb9d3/attachment.html