Hello list, I've imported a new project: http://www.opencores.org/projects.cgi/web/uart16750/overview Well, it's not really 'new' because all big parts are done. But let me explain why I started this project some time ago. I needed a fully compatible 16750 UART core (16750 = 16550 with bigger FIFO and auto flow control but downwards compatible to 16550). It had to be usable with all standard OS 8250/16550 serial drivers, no missing modes or control lines allowed. It was implemented and tested with an Cyclone II and x86 Hardware (Standard PC) via the LPC- and PCI-bus. A script file was written which creates the stimuli file for functional testing (the same file was used to run the tests in simulation and on the real hardware, only another interpreter is required). Whats missing: DMA control lines TXRDY/RXRDY. I forgot these, ups...mostly because it seems no 'standard' OS drivers supports this...? The character timeout counter is using a fixed value. It should be dependent on the mode 5/6/7/8 bits with N/E/O parity. But it seems to have no side-effects on the real-world applications I've tested so far. And there were some nasty real-time applications which are even dependent on the shorter interrupt time difference between the first two characters when the TSR and THR are both empty. Automatic flow control via RTS/CTS. I've started to implement it but it's not completely tested so I wait to check it in. Regards, Sebastian