I've just published a tutorial on creating fast cycle accurate SystemC models using Verilator, using ORPSoC as an example. http://www.embecosm.com/download/ean6.html Verilator is an open source tool, which generates C++ and SystemC cycle accurate models automatically from Verilog RTL (see www.veripool.org/wiki/verilator). The resulting models follow synthesis semantics (2-state, zero delay) and are often considerably quicker than event-driven simulation. I've used the OpenRISC Reference System-on-Chip (SoC) with 2MB flash and 2MB SRAM as an example. An event driven simulation using Icarus Verilog runs at about 1.4kHz on my PC, while the Verilator SystemC model runs at 130kHz. That's quick enough to run useful firmware. I've also hooked the JTAG ports up to GDB via RSP and used it to load and debug software. The tutorial includes complete software examples: http://www.embecosm.com/download/esp5.html Those examples will also be uploaded to OpenCores in the coming days. The tutorial and example code are all free and open source under Creative Commons and GPL licenses. Feedback and comments welcome. I'm particularly interested in comparative performance data from commercial simulators (NC, VCS, ModelSim). Cross-posted to OpenCores and OpenRISC mailing lists, because the subject is of general interest, while the example is OpenRISC. Jeremy -- Tel: +44 (1202) 416955 Cell: +44 (7970) 676050 SkypeID: jeremybennett Email: jeremy.bennett at embecosm.com Web: www.embecosm.com