Hello, I'm a member of the ARMadeus development team, this company designs embedded systems based on ARM processors (i.MX) and FPGA (Spartan) and it's proud to announce the availability of its news card named apf27 (description can be found here :http://www.armadeus.com/english/products-processor_boards-apf27.html). To ease FPGA usage for software developers, a GPL command line tool (POD) has been written which can connect automatically severals "virtual" components together by means of a Wishbone bus. The specification of POD can be found here: http://www.armadeus.com/wiki/index.php?title=POD_specification (from fpga wiki page : http://www.armadeus.com/wiki/index.php?title=Using_FPGA) The main goal of POD is to permit FPGA-newbies to use fpga without writing any VHDL (or verilog) code. The user can choose component he wants in a components library and include it in his project. POD will generate automatically the "glue-files" to produce the FPGA configuration bitstream for the fpga (wishbone intercon, top VHDL hierarchy,tcl script to automatize synthesis, pinout files, ...) and the drivers on the OS side (if component has drivers templates for the OS). The principle of POD is to package HDL components in a directory together with a component description file (XML). Code/Drivers template can be added in to automatize drivers generation for target operating system that will use projects components. Code/driver templates can be easily added Currently few components are integrated in POD: * bram: just for test, instanciate spartan ram * button : manage a user button generating interrupts * led : manage a simple led with a register * simplegpio : a minimalistic input/output manager * irq_mngr : this components manage interrupts from fpga to processor. And some come from opencore: * I2C master * uart16550 POD is designed to be used with other platforms than the Armadeus ones. Actually 3 platforms are supported: 2 ARM-Spartan architectures (Armadeus APF9328 and APF27 boards) and one Atmega-Cyclone architecure named UNIOC POD is also designed to support other bus than Wishbone. Actually POD supports two simples versions of the Wishbone bus: one version with a 16bits data bus (iMX) and an other with a 8 bits data bus (Atmega) The source code of POD is released in GPL and can be found on sourceforge repository: http://periphondemand.sourceforge.net/ It is theoretically usable on any operating system (written in Python) but it has only been tested on a Linux/Debian distribution A use case tutorial can be found on wiki, to explain the usage of POD: http://www.armadeus.com/wiki/index.php?title=POD_Tutorial If you are interested by this project feel free to register on sourceforge mailing list : https://lists.sourceforge.net/lists/listinfo/periphondemand-devel Cheers Fabien Marteau fabien.marteau at armadeus.com -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20090224/09d7b7a0/attachment-0001.htm

Fabien Marteau wrote:


Could be a speed up tool for some purposes. Does it generate intermediate code in VHDL or verilog 2001
to feed into the "external proprietary software" to synthetize and configure the FPGA? VHDL is hinted in fig 2. of the spec.

Your spec says, "several simulation libraries can be used to ease testbench writing." Is icarus verilog one of them?

John Griessen
--
Ecosensory Austin TX

Yes, it speed up component assembly. If your components are ready in
library, you can make a final bitstream fastly.





For this moment, it generate only VHDL intermediate code. But it designed to
be multi-language then Verilog can be added in tool.




Yes, because only VHDL is supported for this moment.

Your spec says, "several simulation libraries can be used to ease testbench
To add a third party simulation software, specific code for the tool must be added in directory periphondemand/toolchain/simulation/. But for this moment POD doesn't generate Verilog code. Fabien Marteau -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20090303/b7747b47/attachment.html