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Re: getting wb_dma testbench through VCS? [PATCH SUPPLIED]
by Unknown on Feb 6, 2004 |
Not available! | ||
I wrote, while trying to compile the wb_dma testbench, about
VCSi errors of the form...
Error-[XMRE] Cross-module reference resolution error
The problem is that there is a 'wb_mast m0(...)' definition
in bench/verilog/test_bench_top.v, but in the `included
tests.v, there is at least one definition of an *integer*
m0. Yurk!
Different simulators do different things. 'cver' gives the
best error messages; VCSi is right to spot a problem but
gives a terrible error message; both icarus and an old
verilog-xl just stagger forward blindly (and the simulations
are completely useless).
Anyway, the attached patch fixes the problem.
At the very end of the patch, there's an ifndef-thing around
the contents of rtl/verilog/wb_dma_defines.v -- the sort of
thing that is standard in C programming. It eliminates some
compiler warnings, and I commend it to you. Keep up the
good work,
Will
PS: Shouldn't there be one or more 'bug reporting'
links/pages/whatever on www.opencores.org?
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Desc: fix m0 bugs + one ifndef
Url : http://www.opencores.org/forums.cgi/cores/attachments/20040206/e00386d1/wb_dma.obj
Cross module resolution failed, token 'wb_wr1'. Originating module 'test'. "tests.v", 1220: m0.wb_wr1((32'hb0000000 + 8'h38), 4'hf, 32'b0); |
Re: getting wb_dma testbench through VCS? [PATCH SUPPLIED]
by Unknown on Feb 6, 2004 |
Not available! | ||
The process is much simpler. You send bug report to the author.
regards, Damjan PS: Shouldn't there be one or more 'bug reporting' links/pages/whatever on www.opencores.org? ---------------------------------------------------------------------------- ----
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