Hi,

Does any one knows how to calculate CRC-32 (Ethernet) in 32 bit quantaties
when the packet length is not a multiple of 32 bits ?

One solution is to have four CRC calculation functions, with input data width
of 8, 16, 24 and 32 bits. Then you calculate the CRC ovr the packet as it
arrives and feed the last data to all modules, but select only the one with
the correct result according to the length of the packet.

Unfortunatly this is a very logic consuming method. Does any one know of a
better solution, that do not require the length of the packet in advance ?

Thanks for any help,
Erez.

Aloha! Quoting Erez Birenzwig erez_birenzwig at yahoo.com>: Not 100% sure what you mean by this. The CRC-32 result/state is indeed 32 bits, but that does not mean that you have to receive 32 bits to update the CRC-32 state. Normally, the CRC-32 generator is updated on the serial stream, or (since the data flowing over the CRC-32 checked links are based on octets) bytes/octets. There are several implementations available for both serial- and byte-wide inputs. The drawback with the serial version is that you (naturally) have to run it at wire-speed, the implementation though requires less registers since you don't need any shift-registers to parallellize/hold the incoming data/operand (which OTOTH you quite probably have in the design) Some god references found by your trusty friend Google. The paper from IBM is really nice. Xilinx Xapp that includes Perl-based Verilog generator of CRC-32 for IEEE 802.3 (Ethernet): http://direct.xilinx.com/bvdocs/appnotes/xapp209.pdf IBM Research journal on efficient CRC-32 implementation for ATM etc: http://www.research.ibm.com/journal/rd/416/glaise.html A nice picture of a CRC-32 LFSR for serial calculation: http://totoro.cs.nthu.edu.tw/course/ppt/chap04/img010.JPG You should never need to know the packet length in advance. The CRC-32 is/should be calculated on the fly. Good luck! --- Joachim Strömbergson - Alltid i harmonisk svängning. VP, Research & Development ---------------------------------------------------------------------- InformAsic AB / Hugo Grauers gata 5B / SE-411 33 GÖTEBORG / Sweden Tel: +46 31 68 54 90 Fax: +46 31 68 54 91 Mobile: +46 733 75 97 02 E-mail: joachim.strombergson at informasic.com Home: www.informasic.com ----------------------------------------------------------------------

see http://www.easics.be/webtools/crctool for ideas. Erez Birenzwig wrote:

Hi Erez,



The complexity for this type of approach depends on
the data path width for which you are trying to
compute CRC. if you are implementing on a 32 bit wide
data path, it is not 'that' worse and can be
reasonable. you may refer the paper below,
"Creating High-performance reusable 10Gigabit Ethernet
MAC designs, Designcon 2003, Santa Clara, CA, USA".

Nobug consulting has an excellent paper on CRC
computation for unaligned data paths without using
above mentioned multiplexing approach.
it can be downloaded from
www.nobugconsulting.com/crc_details.pdf

regards,
Jayaprakash.












===== Balachandran Jayaprakash Celestijnenlaan, 3/61, 3001, Heverlee, Leuven, Belgium. Mobile: +32-472-630120 ___________________________________________________________ Yahoo! Messenger - Communicate instantly..."Ping" your friends today! Download Messenger Now http://uk.messenger.yahoo.com/download/index.html

Hi Jayaprakash, Thanks for the Nobug document, I found it very interesting. It seems like this is what I was looking for. I think I'll be able to extend the code to work on data path of 64 bits and with different polynoms. I wasn't able to read the other article you mentioned and wondered if it's freely available on the web ? Thanks again, Erez. --- Jayaprakash edpc108 at yahoo.com> wrote:

Hi John, That's a good link as long as your data is of constant blocks. My problem is that the data is not constant blocks. I've tried the solution from Nobug, but the logic chain is no acceptable for FPGA design. It's a good idea though. Does any one have other ideas ? Regards, Erez. --- John Sheahan jrsheahan at optushome.com.au> wrote:

The tool gives you combinatorial gates.
You could instantiate all 4 gate sets 98,16,24,32)
and latch the width you require into your 32 bit register each cycle.

Its the synthesis tool's job to minimize it obviously:).
john


Erez Birenzwig wrote:

John, First thanks for your help. This is the solution I'm implementing as it seems nothing else is available and will run at high frequency in a FPGA. Erez. --- John Sheahan jrsheahan at optushome.com.au> wrote:

----- Original Message ----- From: Jayaprakashedpc108 at y...> To: Date: Tue Mar 2 14:10:58 CET 2004 Subject: [oc] CRC32 Calculation
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hi Jasmina .. I am looking for www.nobugconsulting.com/crc_details.pdf. Can you please send it through mail If u have any local copy. ----- Original Message ----- From: jasmina.matjaz at siol.netjasmina.matjaz at s...> To: Date: Fri Jul 2 20:46:06 CEST 2004 Subject: [oc] CRC32 Calculation
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here it is http://web.archive.org/web/20051125200736/http://www.nobugconsulting.com/crc_details.pdf On Sun, Dec 21, 2008 at 4:22 PM, ashish228 at gmail.com> wrote: _______________________________________________ http://www.opencores.org/mailman/listinfo/cores