I am designing a memory controller as a part of my course project. The
size of the memory is 512 bytes. I think I need a 8-bit (data bus)* 1 to
512 Mux for the design. I was surprised seeing the gate count just for
directing the data to the appropriate memory location. Because as the
size of the memory increases the size of the MUX will increase. I would
really appreciate if anyone can let me know if it is the way the design is
implemented in hardware? And what would be the gate equivalent of a
MUX in a typical FPGA/ASIC?

Thanks for your time.