Hi All,

I have started using the “nccov” tool for code coverage of verilog
code.
It is the tool that comes along with NC Verilog. I am getting the
reports
in terms of percentage of statements, expressions and FSMs. But how
to get exactly the reports about the part of the RTL not covered in
the
test bench?

Can anybody suggest some more tools for code coverage?



Thanks in advance,

Regards,

Vlsi Champ....

Hi there, I'm trying to use ncCov as the coverage analyse tool for verilog design. I've put the swith +nccoverage in the simulation. I think this enables the coverage instrumentation. Can anybody advise where I can find the report files(which directory the report files reside)? Do I need to perform other steps in order to get the report? Many thanks, Hong ----- Original Message ----- From: vlsi_champ at i... To: cores at o... Date: Wed, 28 Aug 2002 06:27:55 -0100 Subject: [oc] Code Coverage
coverage of verilog

the

But how

covered in