Hello,

How to implement dynamic memory allocatuion using Verilog?

Where can I get the Verilog code for dynamic memory allocation?
Can anybody give some pointers to some code!

Thanks in advance

Aloha! Quoting abhi_vlsi02 at yahoo.com:

What do you mean with dynamic mem allocation with respect to hardware
implementation? What is the application/purpose?

Is it cache memory, hw-acceleration of an OS or?

I might be wrong, but I don't think there are that many examples of malloc-type implementations in hardware. What you can do is look at processors that implement TLB-support, which normally contains tables/bits to keep track of allocated pages and some sort of control mechanism (i.e. a FSM) to check requested addresses with the allocated pages. A malloc is similar, the difference mainly being: (1) You allocate a requested *number* of pages and hand back the address, not check the address agains allocated pages. (2) You need to handle fragmentation somehow. This is because when you then get free() calls you will end upp with free pages scattered in between allocated pages. The discrete knapsack problem will then unsure that you will not be able to allocate all free space in a given free area, thus leaving more and more single empty pages in between the allocated ones. Basic mem allocation problem. There are possibly opportunities to handle pointer matching, mem fill, mem copy operations in HW thereby gaining CPU performance, and some CPUs do this, but have never seen a complete, full blown malloc() in HW. Anybody else on the OC-list with different experience? -- Med vänlig hälsning, Yours Joachim Strömbergson - Alltid i harmonisk svängning. VP, Research & Development ---------------------------------------------------------------------- InformAsic AB / Hugo Grauers gata 5B / SE-411 33 GÖTEBORG / Sweden Tel: +46 31 68 54 90 Fax: +46 31 68 54 91 Mobile: +46 733 75 97 02 E-mail: joachim.strombergson at informasic.com Home: www.informasic.com ----------------------------------------------------------------------

In case the original issue was regarding Verilog for modelling in
general, this answer might be useful:
You can't. Verilog doesn't have dynamic memory handling built into
the language.

However, you can use the powerful PLI interface to call functions
written in C, including functions using dynamic memory handling.
Of course, this will not be synthesisable in any way, but it is
fine for simulation.

I don't have any reference to code using the PLI laying around, but
the Verilog Language Reference Manual should contain most of the
stuff you need. It used to be available on the net, but from a
quick search I couldn't find it anymore... The filenames are
ovi.verilog.lrm.1.0.pdf and ovi.pli.1.0.pdf if that is of any help.
They can be ordered from the IEEE, www.ieee.org anyway, but probably
at a cost.
Maybe someone else has a good pointer? :)

Regards
Gunnar Dahlgren

At 13:33 2004-03-18 +0100, Joachim Strombergson wrote:

malloc-type

then get

able

copy

On Thu, 2004-03-18 at 19:05, abhi_vlsi02 at yahoo.com wrote: There are many different ways to solve this problem. It really depends what you are trying to do. In case of cashes or MMUs, the good old TLBs are used. If you must allocate internal memory for passing through data blocks for such applications where you have to do bandwidth matching for example, you can simplify the problem. I used a separate piece of memory to hold the pointers and the equivalent of the "malloc header" (of course all optimized for hardware and my specific problem). To avoid fragmentation nightmares, make sure you always allocate memory in fixed min size blocks. If possible only support one block size ... Regards, rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> http://www.asics.ws/