Hi, Elites. Allow a student to inject a trivial question.
When implementing SRL(Shift register) on LUT(Xilinx FPGA), I tried to finding the architecture of LUT, but failed. who can give the schematic of LUT?
Thank you in advance for any info..

Regards

Q.Fang

Aloha! Quoting QFang q_f82 at sina.com>: Xilinx has great data sheets with detailed information about their LUTs for all their FPGAs. Check http://www.xilinx.com. Under the "products & services" you can select the specific device family you are using and then on the right hand side of the page you will find a link called " Data Sheet and User Guide". Traditionally Xilinx always includes nice pictures and detailed text information about the contents of their LUTs, slices and all other resources in their devices. As does Altera, and I'm sure other FPGA/CPLD vendors does to (I've looked at Actel and QuickLogic and so far I have always been able to find this information). The key term here is "data sheet". Good luck! -- Med vänlig hälsning, Yours Joachim Strömbergson - Alltid i harmonisk svängning. VP, Research & Development ---------------------------------------------------------------------- InformAsic AB / Hugo Grauers gata 5B / SE-411 33 GÖTEBORG / Sweden Tel: +46 31 68 54 90 Fax: +46 31 68 54 91 Mobile: +46 733 75 97 02 E-mail: joachim.strombergson at informasic.com Home: www.informasic.com ----------------------------------------------------------------------

The architecture of the LUT should be in the datasheet, isn't it ?
Did I understand your question right?

QFang wrote:

Hi thanks for response! But maybe my poor English make you misunderstand. What I am looking for is the intra-architecture of LUT. I have checked the info. in xilinx product handbook,application notes, white papers, and the schematic in FPGA-editor before, but the LUT was always seen as a black-box. I want to know the detailed circuits in LUT. Is it the patent of the company? (About the intra-architecture of LUT, I know something outdated in MIT A.I technical Report No.1586, named as "Reconfigurable Architectures for General-Purpose Computing". 1996) Regards Loki ----- Original Message ----- From: "Joachim Strombergson" Joachim.Strombergson at InformAsic.com> To: cores at opencores.org>; "QFang" q_f82 at sina.com> Sent: Thursday, April 01, 2004 7:08 PM Subject: Re: [oc]Xilinx FPGA LUT Architecture -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20040402/43f3aedd/attachment.htm

Aloha! Quoting QFang q_f82 at sina.com>:

Que?

and slices, not a black box. As an example, please check (for example) Figure 6 in the Spartan-III functional specification: http://direct.xilinx.com/bvdocs/publications/ds099-2.pdf You can directly see what resources are available within your slice and CLB. The registers, LUTs, carry chain logic etc.

If you mean the actual transistor, switching level implementation of the LUTs
within the CLBs then quite probably yes. They are at least considered trade
secrets (note: IANAL). Efficient transistor level implementation in the given
technology is obviously extremely important if you want to be competetetive in
creating large FPGAs.

(Good microarchitecture is another important issu, just like efficient mapping,
routing etc etc.)

Xilinx, and for that matter Altera and the others prominently lists rows of
patent numbers in their documentation, and I would wager a beer that some of
them are related to efficient CMOS-implementations of reconfigurable MUX
structures.

I would assume however that there would be some papers published about this.
Have you searched siteseer and/or (for example) ISSCC-proceedings? The problem
of making efficient implementations of LUTs and other basic reconfigurable
structures are such a well defined area that it should be good candidates for
VLSI-resarch.

There must be newer articles than that. Happy hunting. -- Med vänlig hälsning, Yours Joachim Strömbergson - Alltid i harmonisk svängning. VP, Research & Development ---------------------------------------------------------------------- InformAsic AB / Hugo Grauers gata 5B / SE-411 33 GÖTEBORG / Sweden Tel: +46 31 68 54 90 Fax: +46 31 68 54 91 Mobile: +46 733 75 97 02 E-mail: joachim.strombergson at informasic.com Home: www.informasic.com ----------------------------------------------------------------------