Hi,cores When I used synopsys tools formality to verify. I found oc8051_int.v has some problem. Is there any body find same problem? .... Status: Elaborating design oc8051_int ... Warning: Index may take values outside array bound, may cause simulation mismatch .. (File: /home/wangjh/temp/work/oc8051/rtl/verilog/oc8051_int.v Line: 119) (FMR_ELAB-147) Warning: Index may take values outside array bound, may cause simulation mismatch .. (File: /home/wangjh/temp/work/oc8051/rtl/verilog/oc8051_int.v Line: 121) (FMR_ELAB-147) Warning: Out of range write possible, may cause simulation and synthesis mismatch. (File: /home/wangjh/temp/work/oc8051/rtl/verilog/oc8051_int.v Line: 300) (FMR_ELAB-146) Warning: Out of range write possible, may cause simulation and synthesis mismatch. (File: /home/wangjh/temp/work/oc8051/rtl/verilog/oc8051_int.v Line: 304) (FMR_ELAB-146) Warning: Out of range write possible, may cause simulation and synthesis mismatch. (File: /home/wangjh/temp/work/oc8051/rtl/verilog/oc8051_int.v Line: 307) (FMR_ELAB-146) Warning: Out of range write possible, may cause simulation and synthesis mismatch. (File: /home/wangjh/temp/work/oc8051/rtl/verilog/oc8051_int.v Line: 310) (FMR_ELAB-146) Warning: Out of range write possible, may cause simulation and synthesis mismatch. (File: /home/wangjh/temp/work/oc8051/rtl/verilog/oc8051_int.v Line: 313) (FMR_ELAB-146) Warning: Out of range write possible, may cause simulation and synthesis mismatch. (File: /home/wangjh/temp/work/oc8051/rtl/verilog/oc8051_int.v Line: 316) (FMR_ELAB-146) Warning: Out of range write possible, may cause simulation and synthesis mismatch. (File: /home/wangjh/temp/work/oc8051/rtl/verilog/oc8051_int.v Line: 319) (FMR_ELAB-146) Warning: Out of range write possible, may cause simulation and synthesis mismatch. (File: /home/wangjh/temp/work/oc8051/rtl/verilog/oc8051_int.v Line: 324) (FMR_ELAB-146) Warning: Out of range write possible, may cause simulation and synthesis mismatch. (File: /home/wangjh/temp/work/oc8051/rtl/verilog/oc8051_int.v Line: 328) (FMR_ELAB-146) Warning: Out of range write possible, may cause simulation and synthesis mismatch. (File: /home/wangjh/temp/work/oc8051/rtl/verilog/oc8051_int.v Line: 331) (FMR_ELAB-146) Warning: Out of range write possible, may cause simulation and synthesis mismatch. (File: /home/wangjh/temp/work/oc8051/rtl/verilog/oc8051_int.v Line: 334) (FMR_ELAB-146) Warning: Out of range write possible, may cause simulation and synthesis mismatch. (File: /home/wangjh/temp/work/oc8051/rtl/verilog/oc8051_int.v Line: 337) (FMR_ELAB-146) Warning: Out of range write possible, may cause simulation and synthesis mismatch. (File: /home/wangjh/temp/work/oc8051/rtl/verilog/oc8051_int.v Line: 340) (FMR_ELAB-146) Warning: Out of range write possible, may cause simulation and synthesis mismatch. (File: /home/wangjh/temp/work/oc8051/rtl/verilog/oc8051_int.v Line: 343) (FMR_ELAB-146) Error: Failed to link design 'oc8051_int' to cell '/WORK/oc8051_sfr/oc8051_int1'. (FM-234) Junhu_Wang/SMIC -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20040406/276aac7d/attachment.htm

This just means the vector used to address an array can take values larder then the array width. It isn't strictly an error. For example let say you have an array which is 13 words deep, you'll need a 4 bit number to address it, but the 4 bit number can address places 14 to 16 as well. Formality only tells you that it may cause problems. Erez. ----- Original Message ----- From: Junhu_Wang To: cores at opencores.org Sent: Tuesday, April 06, 2004 12:48 PM Subject: [oc] oc8051_int.v Out of range write possible,may cause simulation and synthesis mismatch Hi,cores When I used synopsys tools formality to verify. I found oc8051_int.v has some problem. Is there any body find same problem? .... Status: Elaborating design oc8051_int ... Warning: Index may take values outside array bound, may cause simulation mismatch .. (File: /home/wangjh/temp/work/oc8051/rtl/verilog/oc8051_int.v Line: 119) (FMR_ELAB-147) Warning: Index may take values outside array bound, may cause simulation mismatch .. (File: /home/wangjh/temp/work/oc8051/rtl/verilog/oc8051_int.v Line: 121) (FMR_ELAB-147) Warning: Out of range write possible, may cause simulation and synthesis mismatch. (File: /home/wangjh/temp/work/oc8051/rtl/verilog/oc8051_int.v Line: 300) (FMR_ELAB-146) Warning: Out of range write possible, may cause simulation and synthesis mismatch. (File: /home/wangjh/temp/work/oc8051/rtl/verilog/oc8051_int.v Line: 304) (FMR_ELAB-146) Warning: Out of range write possible, may cause simulation and synthesis mismatch. (File: /home/wangjh/temp/work/oc8051/rtl/verilog/oc8051_int.v Line: 307) (FMR_ELAB-146) Warning: Out of range write possible, may cause simulation and synthesis mismatch. (File: /home/wangjh/temp/work/oc8051/rtl/verilog/oc8051_int.v Line: 310) (FMR_ELAB-146) Warning: Out of range write possible, may cause simulation and synthesis mismatch. (File: /home/wangjh/temp/work/oc8051/rtl/verilog/oc8051_int.v Line: 313) (FMR_ELAB-146) Warning: Out of range write possible, may cause simulation and synthesis mismatch. (File: /home/wangjh/temp/work/oc8051/rtl/verilog/oc8051_int.v Line: 316) (FMR_ELAB-146) Warning: Out of range write possible, may cause simulation and synthesis mismatch. (File: /home/wangjh/temp/work/oc8051/rtl/verilog/oc8051_int.v Line: 319) (FMR_ELAB-146) Warning: Out of range write possible, may cause simulation and synthesis mismatch. (File: /home/wangjh/temp/work/oc8051/rtl/verilog/oc8051_int.v Line: 324) (FMR_ELAB-146) Warning: Out of range write possible, may cause simulation and synthesis mismatch. (File: /home/wangjh/temp/work/oc8051/rtl/verilog/oc8051_int.v Line: 328) (FMR_ELAB-146) Warning: Out of range write possible, may cause simulation and synthesis mismatch. (File: /home/wangjh/temp/work/oc8051/rtl/verilog/oc8051_int.v Line: 331) (FMR_ELAB-146) Warning: Out of range write possible, may cause simulation and synthesis mismatch. (File: /home/wangjh/temp/work/oc8051/rtl/verilog/oc8051_int.v Line: 334) (FMR_ELAB-146) Warning: Out of range write possible, may cause simulation and synthesis mismatch. (File: /home/wangjh/temp/work/oc8051/rtl/verilog/oc8051_int.v Line: 337) (FMR_ELAB-146) Warning: Out of range write possible, may cause simulation and synthesis mismatch. (File: /home/wangjh/temp/work/oc8051/rtl/verilog/oc8051_int.v Line: 340) (FMR_ELAB-146) Warning: Out of range write possible, may cause simulation and synthesis mismatch. (File: /home/wangjh/temp/work/oc8051/rtl/verilog/oc8051_int.v Line: 343) (FMR_ELAB-146) Error: Failed to link design 'oc8051_int' to cell '/WORK/oc8051_sfr/oc8051_int1'. (FM-234) Junhu_Wang/SMIC ------------------------------------------------------------------------------ _______________________________________________ http://www.opencores.org/mailman/listinfo/cores -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20040411/d13c54d7/attachment.htm