I would like a recommendation for a book about writing Verilog
testbenches. Does anyone have an opinion on which book they would
consider the best in class?

Books on other topics that I recommend are:

Verilog Quickstart Third Edition by James M. Lee.

This is an excellent book that walks you through most of the capabilities
of the language. It covers some of the features of Verilog 2001, the
notable exception being the generate statement. I bought four copies
of this book for so I could have one at home and enough at work to
share.

Reuse Methodology Manual Third Edition by Michael Keating and Pierre
Bricaud.

This book is the result of a joint project between Synopsys and Mentor
Graphics to study how to help their customers produce and integrate
reusable IP cores. This book should be very relevant to anyone who is
reading OpenCores forums.


Thank you,

John McCaskill

Writing Testbenches
Functional Verification of HDL Models
Janick Bergeron

Not jus verilgo, covers VHDL as well.

Bricaud. This reminds me of the webcast: VSIA Quality Metric for IP (VSIA-QIP) "Can IP Quality Be Objectively Measured?" http://seminar2.techonline.com/~vsia22/dec0903/ I would like to get a hold of the relevant docs from VSIA for my own use, but membership is too expensive. Is there a similar IP quality initiative at Opencores? ------------------------------------------------------------ CONFIDENTIALITY NOTICE This email and any attached documents may be confidential and property of BiTMICRO Networks, Inc. If you are not the intended recipient, you may not disclose, copy, distribute, or act in reliance on the information in this email. Thank you.