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CAN controler
by Unknown on Apr 9, 2004 |
Not available! | ||
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Hi,
Integration of IP CAN in an academic project: I note at the end of the transmission (500kbits/s) in CAN 2.A that I do not find the ACK delimitor (recessif bit) but I find 6 dominant bits. I look this. For the RAM port doubles of Altera, the definition should be modified because there are 2 entries additional (wrclken & rdclken : see the file 220model.v). I 'm not test this modification still. Yann Regards |
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CAN controler
by igorm on Apr 13, 2004 |
igorm
Posts: 5 Joined: Sep 25, 2001 Last seen: Dec 21, 2022 |
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You got an error instead of the acknowledge.
Regards,
Igor
On 4/9/2004, "bozec at iuplo.univ-ubs.fr" bozec at iuplo.univ-ubs.fr> wrote:
Hi,
Integration of IP CAN in an academic project: I note at the end of the
transmission (500kbits/s) in CAN 2.A that I do not find the ACK delimitor
(recessif bit) but I find 6 dominant bits. I look this. For the RAM port
doubles of Altera, the definition should be modified because there are 2
entries additional (wrclken & rdclken : see the file 220model.v). I 'm not
test this modification still.
Yann
Regards
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores
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CAN controler
by Unknown on May 3, 2004 |
Not available! | ||
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Hi,
Well, For resolve a problem of end of frame, I modified can_bsp.v file
and added "|finish_msg" in the Tx_state . Now, the end of frame is oK
in transmission
Regards.
Yann
Below This modification
// Tx state
always @ (posedge clk or posedge rst)
begin
if (rst)
tx_state igorm at m...igorm at m...>
To:
Date: Tue Apr 13 14:16:41 CEST 2004
Subject: [oc] CAN controler
You got an error instead of the acknowledge.
Regards,
Igor
On 4/9/2004, "bozec at i..."
bozec at i...> wrote:
>Hi,
>Integration of IP CAN in an academic project: I note at the end of the
>transmission (500kbits/s) in CAN 2.A that I do not find the ACK
delimitor
>(recessif bit) but I find 6 dominant bits. I look this. For the
RAM port
>doubles of Altera, the definition should be modified because
there are 2
>entries additional (wrclken & rdclken : see the file
220model.v). I 'm not
>test this modification still.
>
>Yann
>
>Regards
>_______________________________________________
>http://www.opencores.org/mailman/listinfo/cores
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CAN controler
by Unknown on May 3, 2004 |
Not available! | ||
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Hi.
What you did is not correct.
You can't reset the tx_state with the finish_msg signal.
Finish_msg is set in the go_rx_crc_lim state and that is way too fast.
Why do you want to change that at all?
Regards,
Igor
-----Izvirno sporoÄilo-----
Od: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org]
Namesto bozec at iuplo.univ-ubs.fr
Poslano: Monday, May 03, 2004 9:13 AM
Za: cores at opencores.org
Zadeva: Re: [oc] CAN controler
Hi,
Well, For resolve a problem of end of frame, I modified can_bsp.v file
and added "|finish_msg" in the Tx_state . Now, the end of frame is oK
in transmission
Regards.
Yann
Below This modification
// Tx state
always @ (posedge clk or posedge rst)
begin
if (rst)
tx_state igorm at m...igorm at m...>
To:
Date: Tue Apr 13 14:16:41 CEST 2004
Subject: [oc] CAN controler
You got an error instead of the acknowledge.
Regards,
Igor
On 4/9/2004, "bozec at i..."
bozec at i...> wrote:
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores
>Hi,
>Integration of IP CAN in an academic project: I note at the end of the
>transmission (500kbits/s) in CAN 2.A that I do not find the ACK
delimitor
>(recessif bit) but I find 6 dominant bits. I look this. For the
RAM port
>doubles of Altera, the definition should be modified because
there are 2
>entries additional (wrclken & rdclken : see the file
220model.v). I 'm not
>test this modification still.
>
>Yann
>
>Regards
>_______________________________________________
>http://www.opencores.org/mailman/listinfo/cores
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