Project Name: AVACS
Purpose of this RFP/RFQ: Development/costing of a
component to be utilized in a "public domain"
(GNU/OpenCore [hardware and software]) DIS/EFI system.
Cost is a major factor [privately funded].
Functionality is a given. If you are car nut, so much
the better.

Current System Design:

MicroController: Atmel ATmega 128 (5V) running at
15MHz. Twenty

(one-shot). Comparator and other timing functions in software. Requirements: 1) Clear and concise documented VHDL code. 2) If selected CPLD/FPGA has "special features" utilized, and VHDL opt-out method/alternative must be defined. Unless, of course, you can convince me a particular device is an absolute gotta-have and won't disappear in the next week .. or two. 3) Buss Interface: The Atmega 128 has 'standard' 16/8 multiplexed buss with Read/Write and ALE. No more, no less. 4) Twenty (60) sixteen-bit count-DOWN counters. One Counter will take input from an encoder (cam/crankshaft) and will reset once every revolution to zero (If possible, doubling the encoder input frequency). The other counters will run at 1/2 of the system clock to determine the pulse width for ignition and injector drivers and will be fired by a signal from .. 5) One of twenty (20) sixteen-bit 'matched' comparators. 6) General idea is to have the crank/cam counter output a value on an internal 'buss'. The comparators will fire the timers on a match. Timer counts down to zero and resets the comparator. The uC will determine the when-and-how-longs. Somewhat like the Motorla TPU function(s)? 7) Inputs would be those required for the uC interface and outputs would be from (I'll say UP To) the sixty (60) timers. 8) No real problem with splitting between multiple devices. Project Info: Have been tinkering with Xilinx ISE and CoolrunnerII development board. Didn't take long to determine it would be awhile (an understatement) before I mastered 'everything' .. assuming I did. Being somewhat of a realist resulted in this RFQ/RFP. In no rush nor dallying, I must define what I am writing to/from and otherwise have my hands full with Wide-Band, ION sensing and a small host of related items. These 'may' migrate to CPLD/FPGA also. Preference is CPLD .. but not a fixed issue. If you want to join in on the project (two of us over the last 5-months), reasonably amiable, perhaps a bit sarcastic and maybe even human, drop me a note. Realize I did not cover everything as doing so would fix things within my narrow view of implementation. Open for alternatives and constructive (non-flaming) critiques. Please submit interest/questions to mp_ctrl at y... . I will direct you to another site for RFQ/RFP submissions (need not be formal). Jim Summers St Louis, Missouri, USA

----- Original Message ----- From: Jim klasix at y... > To: cores at o... Date: Sat, 14 Dec 2002 09:26:02 -0800 (PST) Subject: [oc] New core Request For Proposal/Quotation

> Jim Summers
> St Louis, Missouri, USA