Hello,

In my free time i am looking arround information for this summer
start a project on opencores designing a modular PCB with Altera
devices, either ACEX1K50 oo APEX20K100E, i still reading documentation.

I have been thinking about putting external SRAM, don't know which
one yet, any suggestion ? Well my question goes a little farther, what
timing considerations do i need to take in order to be able to manage
the SRAM from the FPGA ? does the signal goes thru EABs and direct to
the pin (ACEX1K) ?

This is my first design with FPGAs, but i have design some with
microprocessors and microcontrollers, and there, the designer must do
some job to calculate read/write access to memory, where could i find
information about read/write cycles on FPGAs (only in the datasheet ?)

Cheers !