Hello
I am doing a thesis about DSP 16-bit. The project is written by Verilog
HDL, deployed on FPGA Altera and compiled by Quatus II (Altera). Now I
make an interface between DSP and RAM. I try to make an memory
initilization file (.mif) to initilize data and address loading into RAM to
interface with DSP to simulate. I do on Maxplus II very good, but it's
not successful on Quartus II. I have a MIF file but I can not load data
from this file to waveform in Quartus II. Please show me a way to load
initialization data to RAM to simulate or another way to load data and
simulate waveform from a centain data file. Thanks.