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Quick Start on Opensource ASIC design VLSI Tools by Unknown on May 13, 2004			Not available!
I have written a Quick Start Tutorial for Allaince VLSI Tools The Allaince CAD tools are open source VLSI tools that include among others Logic Synthesis and place & route tools for standard cell ASIC design. One standard cell ASIC library is included with the allaince distribution and another can be downloaded from <A HREF="http://www.vlsitechnology.org/">http://www.vlsitechnology.org/</A> The tutorial doesn't go in too much detail about each tool but people familar with FPGA/ASIC design flow should be able to follow what each tool is doing. Explanation of the tools can found on the follwoing website <A HREF="http://www-asim.lip6.fr/recherche/alliance/">http://www-asim.lip6.fr/recherche/alliance/</A> Theres a foundary in France that supports Allaince flow for low volumes as well as high volume req <A HREF="http://cmp.imag.fr/index.html">http://cmp.imag.fr/index.html</A> (I'm not associated with this foundary its just that they support design flow using Allaince tools ) There is this discussion going on about open hardware design etc just thought having an open source ASIC design flow would be good too The tutorial can be downloaded from here <A HREF="http://shehryar.shaheen.tripod.com">http://shehryar.shaheen.tripod.com</A> -------------- next part -------------- An HTML attachment was scrubbed... URL: <A HREF="http://www.opencores.org/forums.cgi/cores/attachments/20040513/3a15207d/attachment.htm">http://www.opencores.org/forums.cgi/cores/attachments/20040513/3a15207d/attachment.htm</A> I have written a Quick Start Tutorial for Allaince VLSI Tools The Allaince CAD tools are open source VLSI tools that include among others Logic Synthesis and place & route tools for standard cell ASIC design. One standard cell ASIC library is included with the allaince distribution and another can be downloaded from http://www.vlsitechnology.org/ The tutorial doesn't go in too much detail about each tool but people familar with FPGA/ASIC design flow should be able to follow what each tool is doing. Explanation of the tools can found on the follwoing website http://www-asim.lip6.fr/recherche/alliance/ Theres a foundary in France that supports Allaince flow for low volumes as well as high volume req http://cmp.imag.fr/index.html (I'm not associated with this foundary its just that they support design flow using Allaince tools ) There is this discussion going on about open hardware design etc just thought having an open source ASIC design flow would be good too The tutorial can be downloaded from here http://shehryar.shaheen.tripod.com -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20040513/3a15207d/attachment.htm

Quick Start on Opensource ASIC design VLSI Tools by Unknown on May 14, 2004			Not available!
> among others Logic Synthesis and place & route tools for standard I've played around some with the Alliance tool set, and this statement is highly misleading. While there are two tools which are called "logic synthesis", they would not be recognized as a synthesis tool by most FPGA/ASIC designers. The Alliance tools can tackle only a very small subset of VHDL, whose level of abstraction is roughly that of a gate level description. Unless something has changed since when I last looked at the tools, they would not be able to synthesize any of the designs found on OpenCores. The back-end tools are much more complete, although I don't believe that they are timing-aware. > among others Logic Synthesis and place & route tools for standard I've played around some with the Alliance tool set, and this statement is highly misleading. While there are two tools which are called "logic synthesis", they would not be recognized as a synthesis tool by most FPGA/ASIC designers. The Alliance tools can tackle only a very small subset of VHDL, whose level of abstraction is roughly that of a gate level description. Unless something has changed since when I last looked at the tools, they would not be able to synthesize any of the designs found on OpenCores. The back-end tools are much more complete, although I don't believe that they are timing-aware.

Quick Start on Opensource ASIC design VLSI Tools by Unknown on May 14, 2004			Not available!
Thats true that Alliance implements a subset of VHDL BUT Theres a front end tools called VASY with it that can take RTL VHDL and change it to the Allaince VHDL subset The tool BOOG (Binding and Optimization on Gates) IS essentially a logic sysnthesis tool for the Allaince subset of VHDL. So when you do VASY->BOOM->BOOG->LOON (BOOM - Bolean Minimization ) (BOOG - Binding and Optimization) (LOON - Local Optimization on nets) That essentially IS logic sysnthesis of standard VHDL RTL aftet this you get a VHDL gatelevel netlist made up with standrad cells from the library sxlib ( sxlib is distributed with Allance) [q]From here OCP (placer for Standar Cells) and OCR (over the Cell router)[/q] or Nero (Negotinting Router) can be used for place and route so my statement was not 'highly misleading' ----- Original Message ----- From: "Guy Hutchison" <<A HREF="http://www.opencores.org/mailman/listinfo/cores">ghutchis at gmail.com</A>> To: "Discussion list about free open source IP cores" <<A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at opencores.org</A>> Sent: Friday, May 14, 2004 7:12 AM Subject: Re: [oc] Quick Start on Opensource ASIC design VLSI Tools [q]> among others Logic Synthesis and place & route tools for standard [/q] I've played around some with the Alliance tool set, and this statement is highly misleading. While there are two tools which are called "logic synthesis", they would not be recognized as a synthesis tool by most FPGA/ASIC designers. The Alliance tools can tackle only a very small subset of VHDL, whose level of abstraction is roughly that of a gate level description. Unless something has changed since when I last looked at the tools, they would not be able to synthesize any of the designs found on OpenCores. The back-end tools are much more complete, although I don't believe that they are timing-aware. _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A>[/q] Thats true that Alliance implements a subset of VHDL BUT Theres a front end tools called VASY with it that can take RTL VHDL and change it to the Allaince VHDL subset The tool BOOG (Binding and Optimization on Gates) IS essentially a logic sysnthesis tool for the Allaince subset of VHDL. So when you do VASY->BOOM->BOOG->LOON (BOOM - Bolean Minimization ) (BOOG - Binding and Optimization) (LOON - Local Optimization on nets) That essentially IS logic sysnthesis of standard VHDL RTL aftet this you get a VHDL gatelevel netlist made up with standrad cells from the library sxlib ( sxlib is distributed with Allance) From here OCP (placer for Standar Cells) and OCR (over the Cell router) or Nero (Negotinting Router) can be used for place and route so my statement was not 'highly misleading' ----- Original Message ----- From: "Guy Hutchison" ghutchis at gmail.com> To: "Discussion list about free open source IP cores" cores at opencores.org> Sent: Friday, May 14, 2004 7:12 AM Subject: Re: [oc] Quick Start on Opensource ASIC design VLSI Tools > among others Logic Synthesis and place & route tools for standard I've played around some with the Alliance tool set, and this statement is highly misleading. While there are two tools which are called "logic synthesis", they would not be recognized as a synthesis tool by most FPGA/ASIC designers. The Alliance tools can tackle only a very small subset of VHDL, whose level of abstraction is roughly that of a gate level description. Unless something has changed since when I last looked at the tools, they would not be able to synthesize any of the designs found on OpenCores. The back-end tools are much more complete, although I don't believe that they are timing-aware. _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

Quick Start on Opensource ASIC design VLSI Tools by Unknown on May 15, 2004			Not available!
[q] That essentially IS logic sysnthesis of standard VHDL RTL aftet this you get a VHDL gatelevel netlist made up with standrad cells from the library sxlib ( sxlib is distributed with Allance)[/q] Unforunately, neither Verilog nor VHDL has ever defined what portion of the language constitutes the synthesizable subset, and so we are left with de facto standards. The bar for this is whatever VHDL code can be accepted by common synthesis tools as Design Compiler and Get2Chip. While VASY does support more constructs than I thought it did, it was unable to translate several VHDL files (from opencores.org) which I have previously compiled with DC. This means that, in practice, unless you are coding specifically for the Alliance tool set, compiling your code with VASY will require rewriting substantial portions of it. My comment about being misleading was that if you make a statement like "tool XXX supports logic synthesis" with no conditions or caveats, anyone looking at the tool will expect it to have roughly the same capabilities and limitations of other tools that support logic synthesis; VASY/BOOM does not meet these criteria. That essentially IS logic sysnthesis of standard VHDL RTL aftet this you get a VHDL gatelevel netlist made up with standrad cells from the library sxlib ( sxlib is distributed with Allance) Unforunately, neither Verilog nor VHDL has ever defined what portion of the language constitutes the synthesizable subset, and so we are left with de facto standards. The bar for this is whatever VHDL code can be accepted by common synthesis tools as Design Compiler and Get2Chip. While VASY does support more constructs than I thought it did, it was unable to translate several VHDL files (from opencores.org) which I have previously compiled with DC. This means that, in practice, unless you are coding specifically for the Alliance tool set, compiling your code with VASY will require rewriting substantial portions of it. My comment about being misleading was that if you make a statement like "tool XXX supports logic synthesis" with no conditions or caveats, anyone looking at the tool will expect it to have roughly the same capabilities and limitations of other tools that support logic synthesis; VASY/BOOM does not meet these criteria.

Quick Start on Opensource ASIC design VLSI Tools by Unknown on May 15, 2004			Not available!
Ofcourse the Alliance tools cannot be compared with Synopsys DC or Cadence Buildgates etc but theses tools have big price tags which the Allaince tools don't. Its common knowledge that free tools may not be wholly at par with the ones that are not free but then this doesn't mean that nomenclature has to be different Icarus Verilog is grouped under 'Verilog Simulator' but because it doesn't have all the features that NC-Verilog or Verilog-XL have it doesn't need to called say 'half-verilog simulator' or something , now does it :) Alliance tools are free and are opensourse and yes they place some amount of restrictions as to the way RTL is written but then RTL is always written with strict rules keeping mind what the synthesis tools will infer from the RTL. Even Design Compiler or some other high end (and not free) tools will not allow for absolute freedom to write what ever construct one feels like that is part of VHDL or Verilog language and the synthesis tools doesn't complain about it and one still might have to do changes in the code to get it synthsized. While they do support a larger synthesizable subset they are neither free nor opensource. ----- Original Message ----- From: "Guy Hutchison" <<A HREF="http://www.opencores.org/mailman/listinfo/cores">ghutchis at gmail.com</A>> To: "Discussion list about free open source IP cores" <<A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at opencores.org</A>> Sent: Saturday, May 15, 2004 7:17 AM Subject: Re: [oc] Quick Start on Opensource ASIC design VLSI Tools [q]> That essentially IS logic sysnthesis of standard VHDL RTL > aftet this you get a VHDL gatelevel netlist made up with > standrad cells from the library sxlib ( sxlib is distributed with[/q] Allance) [q] Unforunately, neither Verilog nor VHDL has ever defined what portion of the language constitutes the synthesizable subset, and so we are left with de facto standards. The bar for this is whatever VHDL code can be accepted by common synthesis tools as Design Compiler and Get2Chip. While VASY does support more constructs than I thought it did, it was unable to translate several VHDL files (from opencores.org) which I have previously compiled with DC. This means that, in practice, unless you are coding specifically for the Alliance tool set, compiling your code with VASY will require rewriting substantial portions of it. My comment about being misleading was that if you make a statement like "tool XXX supports logic synthesis" with no conditions or caveats, anyone looking at the tool will expect it to have roughly the same capabilities and limitations of other tools that support logic synthesis; VASY/BOOM does not meet these criteria. _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A>[/q] Ofcourse the Alliance tools cannot be compared with Synopsys DC or Cadence Buildgates etc but theses tools have big price tags which the Allaince tools don't. Its common knowledge that free tools may not be wholly at par with the ones that are not free but then this doesn't mean that nomenclature has to be different Icarus Verilog is grouped under 'Verilog Simulator' but because it doesn't have all the features that NC-Verilog or Verilog-XL have it doesn't need to called say 'half-verilog simulator' or something , now does it :) Alliance tools are free and are opensourse and yes they place some amount of restrictions as to the way RTL is written but then RTL is always written with strict rules keeping mind what the synthesis tools will infer from the RTL. Even Design Compiler or some other high end (and not free) tools will not allow for absolute freedom to write what ever construct one feels like that is part of VHDL or Verilog language and the synthesis tools doesn't complain about it and one still might have to do changes in the code to get it synthsized. While they do support a larger synthesizable subset they are neither free nor opensource. ----- Original Message ----- From: "Guy Hutchison" ghutchis at gmail.com> To: "Discussion list about free open source IP cores" cores at opencores.org> Sent: Saturday, May 15, 2004 7:17 AM Subject: Re: [oc] Quick Start on Opensource ASIC design VLSI Tools > That essentially IS logic sysnthesis of standard VHDL RTL > aftet this you get a VHDL gatelevel netlist made up with > standrad cells from the library sxlib ( sxlib is distributed with Allance) Unforunately, neither Verilog nor VHDL has ever defined what portion of the language constitutes the synthesizable subset, and so we are left with de facto standards. The bar for this is whatever VHDL code can be accepted by common synthesis tools as Design Compiler and Get2Chip. While VASY does support more constructs than I thought it did, it was unable to translate several VHDL files (from opencores.org) which I have previously compiled with DC. This means that, in practice, unless you are coding specifically for the Alliance tool set, compiling your code with VASY will require rewriting substantial portions of it. My comment about being misleading was that if you make a statement like "tool XXX supports logic synthesis" with no conditions or caveats, anyone looking at the tool will expect it to have roughly the same capabilities and limitations of other tools that support logic synthesis; VASY/BOOM does not meet these criteria. _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

Quick Start on Opensource ASIC design VLSI Tools by bporcella on May 15, 2004			bporcella Posts: 22 Joined: Jan 16, 2004 Last seen: Oct 2, 2007
Guy & Shehryar: I don't want to get involved in semantics and name calling -- but would like to understand (at least at a high level) the potential value of the Allinace toolset. I generally code in verilog -so have some issues there (independent of which subset of VHDL is supported - and how well that subset is documented) -- but my first impression in looking at the toolset has been that there is no support for timing closure. This is a serious deficiency. Am I missing something? bj Porcella <A HREF="http://pages.sbcglobal.net/bporcella/">http://pages.sbcglobal.net/bporcella/</A> ----- Original Message ----- From: "Guy Hutchison" <<A HREF="http://www.opencores.org/mailman/listinfo/cores">ghutchis at gmail.com</A>> To: "Discussion list about free open source IP cores" <<A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at opencores.org</A>> Sent: Thursday, May 13, 2004 11:12 PM Subject: Re: [oc] Quick Start on Opensource ASIC design VLSI Tools [q]> among others Logic Synthesis and place & route tools for standard[/q] I've played around some with the Alliance tool set, and this statement is highly misleading. While there are two tools which are called "logic synthesis", they would not be recognized as a synthesis tool by most FPGA/ASIC designers. The Alliance tools can tackle only a very small subset of VHDL, whose level of abstraction is roughly that of a gate level description. Unless something has changed since when I last looked at the tools, they would not be able to synthesize any of the designs found on OpenCores. The back-end tools are much more complete, although I don't believe that they are timing-aware. _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A>[/q] Guy & Shehryar: I don't want to get involved in semantics and name calling -- but would like to understand (at least at a high level) the potential value of the Allinace toolset. I generally code in verilog -so have some issues there (independent of which subset of VHDL is supported - and how well that subset is documented) -- but my first impression in looking at the toolset has been that there is no support for timing closure. This is a serious deficiency. Am I missing something? bj Porcella http://pages.sbcglobal.net/bporcella/ ----- Original Message ----- From: "Guy Hutchison" ghutchis at gmail.com> To: "Discussion list about free open source IP cores" cores at opencores.org> Sent: Thursday, May 13, 2004 11:12 PM Subject: Re: [oc] Quick Start on Opensource ASIC design VLSI Tools > among others Logic Synthesis and place & route tools for standard I've played around some with the Alliance tool set, and this statement is highly misleading. While there are two tools which are called "logic synthesis", they would not be recognized as a synthesis tool by most FPGA/ASIC designers. The Alliance tools can tackle only a very small subset of VHDL, whose level of abstraction is roughly that of a gate level description. Unless something has changed since when I last looked at the tools, they would not be able to synthesize any of the designs found on OpenCores. The back-end tools are much more complete, although I don't believe that they are timing-aware. _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

Quick Start on Opensource ASIC design VLSI Tools by Unknown on May 15, 2004			Not available!
Timing & Power Analysis tools (HiTas & Yagle) that were part of Alliance are now part of avertec tools (<A HREF="http://www.avertec.com">http://www.avertec.com</A>) and unfortunately not avalble for free now but supported in the alliance design flow. ----- Original Message ----- From: "bporcella" <<A HREF="http://www.opencores.org/mailman/listinfo/cores">bporcella at sbcglobal.net</A>> To: "Discussion list about free open source IP cores" <<A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at opencores.org</A>> Sent: Saturday, May 15, 2004 5:32 PM Subject: Re: [oc] Quick Start on Opensource ASIC design VLSI Tools [q] Guy & Shehryar: I don't want to get involved in semantics and name calling -- but would like to understand (at least at a high level) the potential value of the Allinace toolset. I generally code in verilog -so have some issues there (independent of which subset of VHDL is supported - and how well that subset is documented) -- but my first impression in looking at the toolset has been that there is no support for timing closure. This is a serious deficiency. Am I missing something? bj Porcella <A HREF="http://pages.sbcglobal.net/bporcella/">http://pages.sbcglobal.net/bporcella/</A> ----- Original Message ----- From: "Guy Hutchison" <<A HREF="http://www.opencores.org/mailman/listinfo/cores">ghutchis at gmail.com</A>> To: "Discussion list about free open source IP cores"[/q] <<A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at opencores.org</A>> [q] Sent: Thursday, May 13, 2004 11:12 PM Subject: Re: [oc] Quick Start on Opensource ASIC design VLSI Tools [q] > among others Logic Synthesis and place & route tools for standard[/q] > > I've played around some with the Alliance tool set, and this statement > is highly misleading. While there are two tools which are called > "logic synthesis", they would not be recognized as a synthesis tool by > most FPGA/ASIC designers. > > The Alliance tools can tackle only a very small subset of VHDL, whose > level of abstraction is roughly that of a gate level description. > Unless something has changed since when I last looked at the tools, > they would not be able to synthesize any of the designs found on > OpenCores. > > The back-end tools are much more complete, although I don't believe > that they are timing-aware. > _______________________________________________ > <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A>[/q] _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A>[/q] Timing & Power Analysis tools (HiTas & Yagle) that were part of Alliance are now part of avertec tools (http://www.avertec.com) and unfortunately not avalble for free now but supported in the alliance design flow. ----- Original Message ----- From: "bporcella" bporcella at sbcglobal.net> To: "Discussion list about free open source IP cores" cores at opencores.org> Sent: Saturday, May 15, 2004 5:32 PM Subject: Re: [oc] Quick Start on Opensource ASIC design VLSI Tools Guy & Shehryar: I don't want to get involved in semantics and name calling -- but would like to understand (at least at a high level) the potential value of the Allinace toolset. I generally code in verilog -so have some issues there (independent of which subset of VHDL is supported - and how well that subset is documented) -- but my first impression in looking at the toolset has been that there is no support for timing closure. This is a serious deficiency. Am I missing something? bj Porcella http://pages.sbcglobal.net/bporcella/ ----- Original Message ----- From: "Guy Hutchison" ghutchis at gmail.com> To: "Discussion list about free open source IP cores" cores at opencores.org> Sent: Thursday, May 13, 2004 11:12 PM Subject: Re: [oc] Quick Start on Opensource ASIC design VLSI Tools > among others Logic Synthesis and place & route tools for standard > > I've played around some with the Alliance tool set, and this statement > is highly misleading. While there are two tools which are called > "logic synthesis", they would not be recognized as a synthesis tool by > most FPGA/ASIC designers. > > The Alliance tools can tackle only a very small subset of VHDL, whose > level of abstraction is roughly that of a gate level description. > Unless something has changed since when I last looked at the tools, > they would not be able to synthesize any of the designs found on > OpenCores. > > The back-end tools are much more complete, although I don't believe > that they are timing-aware. > _______________________________________________ > http://www.opencores.org/mailman/listinfo/cores _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

Quick Start on Opensource ASIC design VLSI Tools by Unknown on May 16, 2004			Not available!
On Sat, 15 May 2004 16:10:09 +0100, Shehryar Shaheen <<A HREF="http://www.opencores.org/mailman/listinfo/cores">shehryar.shaheen at ul.ie</A>> wrote: [q] Ofcourse the Alliance tools cannot be compared with Synopsys DC or Cadence Buildgates etc but theses tools have big price tags which the Allaince tools don't. Its common knowledge that free tools may not be wholly at par with the ones that are not free but then this doesn't mean that nomenclature has to be different[/q] True, but there are also many open-source tools (not, unfortunately, in the EDA space) which are fully the equal of their closed-source equivalents. Your original email implied that Alliance is a production-ready synthesis tool; in my opinion, this is not true. [q] Icarus Verilog is grouped under 'Verilog Simulator' but because it doesn't have all the features that NC-Verilog or Verilog-XL have it doesn't need to called say 'half-verilog simulator' or something , now does it :)[/q] No, but it was usually referred to as an "under development" Verilog simulator in its earlier days. And mostly what I was trying to point out is that Alliance is a synthesis tool, with caveats, and that the caveats are sufficiently large to preclude its use for most things outside of academic research (unless there's a static timing tool in the set that I haven't found yet). Lest you think I am all negative on the subject, some tools that I think are production ready tools are CVer (Verilog simulator), Dinotrace (waveform viewer) and Verilator (Verilog-to-C translator). On Sat, 15 May 2004 16:10:09 +0100, Shehryar Shaheen shehryar.shaheen at ul.ie> wrote: Ofcourse the Alliance tools cannot be compared with Synopsys DC or Cadence Buildgates etc but theses tools have big price tags which the Allaince tools don't. Its common knowledge that free tools may not be wholly at par with the ones that are not free but then this doesn't mean that nomenclature has to be different True, but there are also many open-source tools (not, unfortunately, in the EDA space) which are fully the equal of their closed-source equivalents. Your original email implied that Alliance is a production-ready synthesis tool; in my opinion, this is not true. Icarus Verilog is grouped under 'Verilog Simulator' but because it doesn't have all the features that NC-Verilog or Verilog-XL have it doesn't need to called say 'half-verilog simulator' or something , now does it :) No, but it was usually referred to as an "under development" Verilog simulator in its earlier days. And mostly what I was trying to point out is that Alliance is a synthesis tool, with caveats, and that the caveats are sufficiently large to preclude its use for most things outside of academic research (unless there's a static timing tool in the set that I haven't found yet). Lest you think I am all negative on the subject, some tools that I think are production ready tools are CVer (Verilog simulator), Dinotrace (waveform viewer) and Verilator (Verilog-to-C translator).

Quick Start on Opensource ASIC design VLSI Tools by Unknown on May 16, 2004			Not available!
----- Original Message ----- From: "Guy Hutchison" <<A HREF="http://www.opencores.org/mailman/listinfo/cores">ghutchis at gmail.com</A>> To: "Discussion list about free open source IP cores" <<A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at opencores.org</A>> Sent: Sunday, May 16, 2004 7:24 AM Subject: Re: [oc] Quick Start on Opensource ASIC design VLSI Tools [q] On Sat, 15 May 2004 16:10:09 +0100, Shehryar Shaheen <<A HREF="http://www.opencores.org/mailman/listinfo/cores">shehryar.shaheen at ul.ie</A>> wrote: [q]> > Ofcourse the Alliance tools cannot be compared with Synopsys DC > or Cadence Buildgates etc but theses tools have big price tags which > the Allaince tools don't. Its common knowledge that free tools may > not be wholly at par with the ones that are not free but then this > doesn't mean that nomenclature has to be different[/q] True, but there are also many open-source tools (not, unfortunately, in the EDA space) which are fully the equal of their closed-source equivalents. Your original email implied that Alliance is a production-ready synthesis tool; in my opinion, this is not true.[/q] Well then your opionion is wrong, what my orignal mail implied was correct A synthesis toolset cannot be not-production-ready and be supported by a foundry too. Allaince tools are supported by CMP [q] [q]> Icarus Verilog is grouped under 'Verilog Simulator' but because > it doesn't have all the features that NC-Verilog or Verilog-XL have > it doesn't need to called say 'half-verilog simulator' or something ,[/q] now [q]> does it :)[/q] No, but it was usually referred to as an "under development" Verilog simulator in its earlier days. And mostly what I was trying to point out is that Alliance is a synthesis tool, with caveats, and that the caveats are sufficiently large to preclude its use for most things outside of academic research (unless there's a static timing tool in the set that I haven't found yet).[/q] Static Timing Analysis tool in the Allaince distribution was HiTas thats not avaiable for free now but is supported in the design flow. The tools is avaible from Avertec (www.avertec.com) [q] Lest you think I am all negative on the subject, some tools that I think are production ready tools are CVer (Verilog simulator), Dinotrace (waveform viewer) and Verilator (Verilog-to-C translator). _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A>[/q] ----- Original Message ----- From: "Guy Hutchison" ghutchis at gmail.com> To: "Discussion list about free open source IP cores" cores at opencores.org> Sent: Sunday, May 16, 2004 7:24 AM Subject: Re: [oc] Quick Start on Opensource ASIC design VLSI Tools On Sat, 15 May 2004 16:10:09 +0100, Shehryar Shaheen shehryar.shaheen at ul.ie> wrote: > > Ofcourse the Alliance tools cannot be compared with Synopsys DC > or Cadence Buildgates etc but theses tools have big price tags which > the Allaince tools don't. Its common knowledge that free tools may > not be wholly at par with the ones that are not free but then this > doesn't mean that nomenclature has to be different True, but there are also many open-source tools (not, unfortunately, in the EDA space) which are fully the equal of their closed-source equivalents. Your original email implied that Alliance is a production-ready synthesis tool; in my opinion, this is not true. Well then your opionion is wrong, what my orignal mail implied was correct A synthesis toolset cannot be not-production-ready and be supported by a foundry too. Allaince tools are supported by CMP > Icarus Verilog is grouped under 'Verilog Simulator' but because > it doesn't have all the features that NC-Verilog or Verilog-XL have > it doesn't need to called say 'half-verilog simulator' or something , now > does it :) No, but it was usually referred to as an "under development" Verilog simulator in its earlier days. And mostly what I was trying to point out is that Alliance is a synthesis tool, with caveats, and that the caveats are sufficiently large to preclude its use for most things outside of academic research (unless there's a static timing tool in the set that I haven't found yet). Static Timing Analysis tool in the Allaince distribution was HiTas thats not avaiable for free now but is supported in the design flow. The tools is avaible from Avertec (www.avertec.com) Lest you think I am all negative on the subject, some tools that I think are production ready tools are CVer (Verilog simulator), Dinotrace (waveform viewer) and Verilator (Verilog-to-C translator). _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

Quick Start on Opensource ASIC design VLSI Tools by Unknown on May 16, 2004			Not available!
[q] Well then your opionion is wrong, what my orignal mail implied was correct[/q] I stand corrected. Well then your opionion is wrong, what my orignal mail implied was correct I stand corrected.

Quick Start on Opensource ASIC design VLSI Tools by Unknown on May 16, 2004			Not available!
On Sun, 2004-05-16 at 22:00, Shehryar Shaheen wrote: [q] ----- Original Message ----- From: "Guy Hutchison" <<A HREF="http://www.opencores.org/mailman/listinfo/cores">ghutchis at gmail.com</A>> To: "Discussion list about free open source IP cores" <<A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at opencores.org</A>> Sent: Sunday, May 16, 2004 7:24 AM Subject: Re: [oc] Quick Start on Opensource ASIC design VLSI Tools [q]> On Sat, 15 May 2004 16:10:09 +0100, Shehryar Shaheen > <<A HREF="http://www.opencores.org/mailman/listinfo/cores">shehryar.shaheen at ul.ie</A>> wrote: [q] > > Ofcourse the Alliance tools cannot be compared with Synopsys DC > or Cadence Buildgates etc but theses tools have big price tags which > the Allaince tools don't. Its common knowledge that free tools may > not be wholly at par with the ones that are not free but then this > doesn't mean that nomenclature has to be different[/q] > > True, but there are also many open-source tools (not, unfortunately, > in the EDA space) which are fully the equal of their closed-source > equivalents. Your original email implied that Alliance is a > production-ready synthesis tool; in my opinion, this is not true.[/q] Well then your opionion is wrong, what my orignal mail implied was correct A synthesis toolset cannot be not-production-ready and be supported by a foundry too. Allaince tools are supported by CMP[/q] Perhaps a good way to settle this argument is by using metrics similar used by John Cooley of the Synopsys User Group (SNUG): - How many successful tape-outs where done with the Allaince tools ? - How many where commercial products (vs. educational) ? [q] > Icarus Verilog is grouped under 'Verilog Simulator' but because > it doesn't have all the features that NC-Verilog or Verilog-XL have > it doesn't need to called say 'half-verilog simulator' or something ,[/q] now [q] > does it :)[/q] > > No, but it was usually referred to as an "under development" Verilog > simulator in its earlier days. And mostly what I was trying to point > out is that Alliance is a synthesis tool, with caveats, and that the > caveats are sufficiently large to preclude its use for most things > outside of academic research (unless there's a static timing tool in > the set that I haven't found yet).[/q] Static Timing Analysis tool in the Allaince distribution was HiTas thats not avaiable for free now but is supported in the design flow. The tools is avaible from Avertec (www.avertec.com)[/q] So there is no Timing Analysis tool included in the Alaince tool set, correct ? So that makes the Alaince tools "very limited" to say it in a nice way ... Just because the Alaince tools support a commercial tool does not make them complete or useful. I can use Synopsys Design compiler as part of a Cadance or Mentor design flow ... [q]> Lest you think I am all negative on the subject, some tools that I > think are production ready tools are CVer (Verilog simulator), > Dinotrace (waveform viewer) and Verilator (Verilog-to-C translator).[/q] Regards, rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> <A HREF="http://www.asics.ws/">http://www.asics.ws/</A> <- FREE EDA Tools On Sun, 2004-05-16 at 22:00, Shehryar Shaheen wrote: ----- Original Message ----- From: "Guy Hutchison" ghutchis at gmail.com> To: "Discussion list about free open source IP cores" cores at opencores.org> Sent: Sunday, May 16, 2004 7:24 AM Subject: Re: [oc] Quick Start on Opensource ASIC design VLSI Tools > On Sat, 15 May 2004 16:10:09 +0100, Shehryar Shaheen > shehryar.shaheen at ul.ie> wrote: > > Ofcourse the Alliance tools cannot be compared with Synopsys DC > or Cadence Buildgates etc but theses tools have big price tags which > the Allaince tools don't. Its common knowledge that free tools may > not be wholly at par with the ones that are not free but then this > doesn't mean that nomenclature has to be different > > True, but there are also many open-source tools (not, unfortunately, > in the EDA space) which are fully the equal of their closed-source > equivalents. Your original email implied that Alliance is a > production-ready synthesis tool; in my opinion, this is not true. Well then your opionion is wrong, what my orignal mail implied was correct A synthesis toolset cannot be not-production-ready and be supported by a foundry too. Allaince tools are supported by CMP Perhaps a good way to settle this argument is by using metrics similar used by John Cooley of the Synopsys User Group (SNUG): - How many successful tape-outs where done with the Allaince tools ? - How many where commercial products (vs. educational) ? > Icarus Verilog is grouped under 'Verilog Simulator' but because > it doesn't have all the features that NC-Verilog or Verilog-XL have > it doesn't need to called say 'half-verilog simulator' or something , now > does it :) > > No, but it was usually referred to as an "under development" Verilog > simulator in its earlier days. And mostly what I was trying to point > out is that Alliance is a synthesis tool, with caveats, and that the > caveats are sufficiently large to preclude its use for most things > outside of academic research (unless there's a static timing tool in > the set that I haven't found yet). Static Timing Analysis tool in the Allaince distribution was HiTas thats not avaiable for free now but is supported in the design flow. The tools is avaible from Avertec (www.avertec.com) So there is no Timing Analysis tool included in the Alaince tool set, correct ? So that makes the Alaince tools "very limited" to say it in a nice way ... Just because the Alaince tools support a commercial tool does not make them complete or useful. I can use Synopsys Design compiler as part of a Cadance or Mentor design flow ... > Lest you think I am all negative on the subject, some tools that I > think are production ready tools are CVer (Verilog simulator), > Dinotrace (waveform viewer) and Verilator (Verilog-to-C translator). Regards, rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> http://www.asics.ws/

Quick Start on Opensource ASIC design VLSI Tools by Unknown on May 16, 2004			Not available!
----- Original Message ----- From: "Rudolf Usselmann" <<A HREF="http://www.opencores.org/mailman/listinfo/cores">rudi at asics.ws</A>> To: "Discussion list about free open source IP cores" <<A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at opencores.org</A>> Sent: Sunday, May 16, 2004 5:31 PM Subject: Re: [oc] Quick Start on Opensource ASIC design VLSI Tools [q] On Sun, 2004-05-16 at 22:00, Shehryar Shaheen wrote: [q]> ----- Original Message ----- > From: "Guy Hutchison" <<A HREF="http://www.opencores.org/mailman/listinfo/cores">ghutchis at gmail.com</A>> > To: "Discussion list about free open source IP cores"[/q] <<A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at opencores.org</A>> [q]> Sent: Sunday, May 16, 2004 7:24 AM > Subject: Re: [oc] Quick Start on Opensource ASIC design VLSI Tools > > [q] > On Sat, 15 May 2004 16:10:09 +0100, Shehryar Shaheen > <<A HREF="http://www.opencores.org/mailman/listinfo/cores">shehryar.shaheen at ul.ie</A>> wrote: [q]> > > > Ofcourse the Alliance tools cannot be compared with Synopsys DC > > or Cadence Buildgates etc but theses tools have big price tags which > > the Allaince tools don't. Its common knowledge that free tools may > > not be wholly at par with the ones that are not free but then this > > doesn't mean that nomenclature has to be different[/q] > > True, but there are also many open-source tools (not, unfortunately, > in the EDA space) which are fully the equal of their closed-source > equivalents. Your original email implied that Alliance is a > production-ready synthesis tool; in my opinion, this is not true.[/q] > > Well then your opionion is wrong, what my orignal mail implied was > correct > > A synthesis toolset cannot be not-production-ready and be supported > by a foundry too. Allaince tools are supported by CMP[/q] Perhaps a good way to settle this argument is by using metrics similar used by John Cooley of the Synopsys User Group (SNUG): - How many successful tape-outs where done with the Allaince tools ? - How many where commercial products (vs. educational) ? [q]> > Icarus Verilog is grouped under 'Verilog Simulator' but because > > it doesn't have all the features that NC-Verilog or Verilog-XL have > > it doesn't need to called say 'half-verilog simulator' or something[/q] , [q]> now [q]> > does it :)[/q] > > No, but it was usually referred to as an "under development" Verilog > simulator in its earlier days. And mostly what I was trying to point > out is that Alliance is a synthesis tool, with caveats, and that the > caveats are sufficiently large to preclude its use for most things > outside of academic research (unless there's a static timing tool in > the set that I haven't found yet).[/q] > > Static Timing Analysis tool in the Allaince distribution was HiTas thats > not avaiable for free now but is supported in the design flow. The > tools is avaible from Avertec (www.avertec.com)[/q] So there is no Timing Analysis tool included in the Alaince tool set, correct ? So that makes the Alaince tools "very limited" to say it in a nice way ... Just because the Alaince tools support a commercial tool does not make them complete or useful. I can use Synopsys Design compiler as part of a Cadance or Mentor design flow ...[/q] The alliance tools are there , you don't have to use them or like them or anything to do with them even remotely ok Peace :) [q] [q] > Lest you think I am all negative on the subject, some tools that I > think are production ready tools are CVer (Verilog simulator), > Dinotrace (waveform viewer) and Verilator (Verilog-to-C translator).[/q] Regards, rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> <A HREF="http://www.asics.ws/">http://www.asics.ws/</A> <- FREE EDA Tools _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A>[/q] ----- Original Message ----- From: "Rudolf Usselmann" rudi at asics.ws> To: "Discussion list about free open source IP cores" cores at opencores.org> Sent: Sunday, May 16, 2004 5:31 PM Subject: Re: [oc] Quick Start on Opensource ASIC design VLSI Tools On Sun, 2004-05-16 at 22:00, Shehryar Shaheen wrote: > ----- Original Message ----- > From: "Guy Hutchison" ghutchis at gmail.com> > To: "Discussion list about free open source IP cores" cores at opencores.org> > Sent: Sunday, May 16, 2004 7:24 AM > Subject: Re: [oc] Quick Start on Opensource ASIC design VLSI Tools > > > On Sat, 15 May 2004 16:10:09 +0100, Shehryar Shaheen > shehryar.shaheen at ul.ie> wrote: > > > > Ofcourse the Alliance tools cannot be compared with Synopsys DC > > or Cadence Buildgates etc but theses tools have big price tags which > > the Allaince tools don't. Its common knowledge that free tools may > > not be wholly at par with the ones that are not free but then this > > doesn't mean that nomenclature has to be different > > True, but there are also many open-source tools (not, unfortunately, > in the EDA space) which are fully the equal of their closed-source > equivalents. Your original email implied that Alliance is a > production-ready synthesis tool; in my opinion, this is not true. > > Well then your opionion is wrong, what my orignal mail implied was > correct > > A synthesis toolset cannot be not-production-ready and be supported > by a foundry too. Allaince tools are supported by CMP Perhaps a good way to settle this argument is by using metrics similar used by John Cooley of the Synopsys User Group (SNUG): - How many successful tape-outs where done with the Allaince tools ? - How many where commercial products (vs. educational) ? > > Icarus Verilog is grouped under 'Verilog Simulator' but because > > it doesn't have all the features that NC-Verilog or Verilog-XL have > > it doesn't need to called say 'half-verilog simulator' or something , > now > > does it :) > > No, but it was usually referred to as an "under development" Verilog > simulator in its earlier days. And mostly what I was trying to point > out is that Alliance is a synthesis tool, with caveats, and that the > caveats are sufficiently large to preclude its use for most things > outside of academic research (unless there's a static timing tool in > the set that I haven't found yet). > > Static Timing Analysis tool in the Allaince distribution was HiTas thats > not avaiable for free now but is supported in the design flow. The > tools is avaible from Avertec (www.avertec.com) So there is no Timing Analysis tool included in the Alaince tool set, correct ? So that makes the Alaince tools "very limited" to say it in a nice way ... Just because the Alaince tools support a commercial tool does not make them complete or useful. I can use Synopsys Design compiler as part of a Cadance or Mentor design flow ... The alliance tools are there , you don't have to use them or like them or anything to do with them even remotely ok Peace :) > Lest you think I am all negative on the subject, some tools that I > think are production ready tools are CVer (Verilog simulator), > Dinotrace (waveform viewer) and Verilator (Verilog-to-C translator). Regards, rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> http://www.asics.ws/ http://www.opencores.org/mailman/listinfo/cores

Quick Start on Opensource ASIC design VLSI Tools by bporcella on May 16, 2004			bporcella Posts: 22 Joined: Jan 16, 2004 Last seen: Oct 2, 2007
All: A couple of things pop out of this discussion: 1) A complete -and free - backend solution is of great interest to all of us. 2) Alliance may be the closest thing we have (I haven't seen better alternatives proposed). How much work is it to build a useful timing tool? A primitive approach using verification suites and netlists with gate timing files and average wire load models should be pretty easy to put together. The kind of thing one gets out of DC - using netlist data only, does not seem (at least to me) as difficult a problem to solve as some that have already been solved. I guess it would be nice to have a free primetime or einstimer -- but for a lot of purposes, a somewhat less precise (and so more conservative) approach might be sufficient. Any thoughts from any of you that know more about this stuff??? bj bj Porcella <A HREF="http://pages.sbcglobal.net/bporcella/">http://pages.sbcglobal.net/bporcella/</A> ----- Original Message ----- From: "Shehryar Shaheen" <<A HREF="http://www.opencores.org/mailman/listinfo/cores">shehryar.shaheen at ul.ie</A>> To: <<A HREF="http://www.opencores.org/mailman/listinfo/cores">rudi at asics.ws</A>>; "Discussion list about free open source IP cores" <<A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at opencores.org</A>> Sent: Sunday, May 16, 2004 10:26 AM Subject: Re: [oc] Quick Start on Opensource ASIC design VLSI Tools [q] ----- Original Message ----- From: "Rudolf Usselmann" <<A HREF="http://www.opencores.org/mailman/listinfo/cores">rudi at asics.ws</A>> To: "Discussion list about free open source IP cores"[/q] <<A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at opencores.org</A>> [q] Sent: Sunday, May 16, 2004 5:31 PM Subject: Re: [oc] Quick Start on Opensource ASIC design VLSI Tools [q]> On Sun, 2004-05-16 at 22:00, Shehryar Shaheen wrote: [q] > ----- Original Message ----- > From: "Guy Hutchison" <<A HREF="http://www.opencores.org/mailman/listinfo/cores">ghutchis at gmail.com</A>> > To: "Discussion list about free open source IP cores"[/q] <<A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at opencores.org</A>> [q] > Sent: Sunday, May 16, 2004 7:24 AM > Subject: Re: [oc] Quick Start on Opensource ASIC design VLSI Tools > > [q]> > On Sat, 15 May 2004 16:10:09 +0100, Shehryar Shaheen > > <<A HREF="http://www.opencores.org/mailman/listinfo/cores">shehryar.shaheen at ul.ie</A>> wrote: [q] > > > > Ofcourse the Alliance tools cannot be compared with Synopsys DC > > or Cadence Buildgates etc but theses tools have big price tags[/q] which [q] > > the Allaince tools don't. Its common knowledge that free tools[/q] may [q] > > not be wholly at par with the ones that are not free but then[/q] this [q] > > doesn't mean that nomenclature has to be different[/q] > > > > True, but there are also many open-source tools (not, unfortunately, > > in the EDA space) which are fully the equal of their closed-source > > equivalents. Your original email implied that Alliance is a > > production-ready synthesis tool; in my opinion, this is not true.[/q] > > Well then your opionion is wrong, what my orignal mail implied was > correct > > A synthesis toolset cannot be not-production-ready and be supported > by a foundry too. Allaince tools are supported by CMP[/q] > > > Perhaps a good way to settle this argument is by using > metrics similar used by John Cooley of the Synopsys User > Group (SNUG): > > - How many successful tape-outs where done with > the Allaince tools ? > - How many where commercial products (vs. educational) ? > [q] > > Icarus Verilog is grouped under 'Verilog Simulator' but because > > it doesn't have all the features that NC-Verilog or Verilog-XL[/q] have [q] > > it doesn't need to called say 'half-verilog simulator' or[/q] something [q] , [q] > now [q] > > does it :)[/q] > > > > No, but it was usually referred to as an "under development" Verilog > > simulator in its earlier days. And mostly what I was trying to[/q] point [q]> > out is that Alliance is a synthesis tool, with caveats, and that the > > caveats are sufficiently large to preclude its use for most things > > outside of academic research (unless there's a static timing tool in > > the set that I haven't found yet).[/q] > > Static Timing Analysis tool in the Allaince distribution was HiTas[/q] thats [q] > not avaiable for free now but is supported in the design flow. The > tools is avaible from Avertec (www.avertec.com)[/q] > > So there is no Timing Analysis tool included in the Alaince > tool set, correct ? So that makes the Alaince tools "very > limited" to say it in a nice way ... > > Just because the Alaince tools support a commercial tool does > not make them complete or useful. I can use Synopsys Design > compiler as part of a Cadance or Mentor design flow ...[/q] The alliance tools are there , you don't have to use them or like them or anything to do with them even remotely ok Peace :) [q]> [q]> > Lest you think I am all negative on the subject, some tools that I > > think are production ready tools are CVer (Verilog simulator), > > Dinotrace (waveform viewer) and Verilator (Verilog-to-C translator).[/q] > > Regards, > rudi > ======================================================== > ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: > ..............::: FPGAs * Full Custom ICs * IP Cores ::: > FREE IP Cores -> <A HREF="http://www.asics.ws/">http://www.asics.ws/</A> <- FREE EDA Tools > > > _______________________________________________ > <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A>[/q] _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A>[/q] All: A couple of things pop out of this discussion: 1) A complete -and free - backend solution is of great interest to all of us. 2) Alliance may be the closest thing we have (I haven't seen better alternatives proposed). How much work is it to build a useful timing tool? A primitive approach using verification suites and netlists with gate timing files and average wire load models should be pretty easy to put together. The kind of thing one gets out of DC - using netlist data only, does not seem (at least to me) as difficult a problem to solve as some that have already been solved. I guess it would be nice to have a free primetime or einstimer -- but for a lot of purposes, a somewhat less precise (and so more conservative) approach might be sufficient. Any thoughts from any of you that know more about this stuff??? bj bj Porcella http://pages.sbcglobal.net/bporcella/ ----- Original Message ----- From: "Shehryar Shaheen" shehryar.shaheen at ul.ie> To: rudi at asics.ws>; "Discussion list about free open source IP cores" cores at opencores.org> Sent: Sunday, May 16, 2004 10:26 AM Subject: Re: [oc] Quick Start on Opensource ASIC design VLSI Tools ----- Original Message ----- From: "Rudolf Usselmann" rudi at asics.ws> To: "Discussion list about free open source IP cores" cores at opencores.org> Sent: Sunday, May 16, 2004 5:31 PM Subject: Re: [oc] Quick Start on Opensource ASIC design VLSI Tools > On Sun, 2004-05-16 at 22:00, Shehryar Shaheen wrote: > ----- Original Message ----- > From: "Guy Hutchison" ghutchis at gmail.com> > To: "Discussion list about free open source IP cores" cores at opencores.org> > Sent: Sunday, May 16, 2004 7:24 AM > Subject: Re: [oc] Quick Start on Opensource ASIC design VLSI Tools > > > > On Sat, 15 May 2004 16:10:09 +0100, Shehryar Shaheen > > shehryar.shaheen at ul.ie> wrote: > > > > Ofcourse the Alliance tools cannot be compared with Synopsys DC > > or Cadence Buildgates etc but theses tools have big price tags which > > the Allaince tools don't. Its common knowledge that free tools may > > not be wholly at par with the ones that are not free but then this > > doesn't mean that nomenclature has to be different > > > > True, but there are also many open-source tools (not, unfortunately, > > in the EDA space) which are fully the equal of their closed-source > > equivalents. Your original email implied that Alliance is a > > production-ready synthesis tool; in my opinion, this is not true. > > Well then your opionion is wrong, what my orignal mail implied was > correct > > A synthesis toolset cannot be not-production-ready and be supported > by a foundry too. Allaince tools are supported by CMP > > > Perhaps a good way to settle this argument is by using > metrics similar used by John Cooley of the Synopsys User > Group (SNUG): > > - How many successful tape-outs where done with > the Allaince tools ? > - How many where commercial products (vs. educational) ? > > > Icarus Verilog is grouped under 'Verilog Simulator' but because > > it doesn't have all the features that NC-Verilog or Verilog-XL have > > it doesn't need to called say 'half-verilog simulator' or something , > now > > does it :) > > > > No, but it was usually referred to as an "under development" Verilog > > simulator in its earlier days. And mostly what I was trying to point > > out is that Alliance is a synthesis tool, with caveats, and that the > > caveats are sufficiently large to preclude its use for most things > > outside of academic research (unless there's a static timing tool in > > the set that I haven't found yet). > > Static Timing Analysis tool in the Allaince distribution was HiTas thats > not avaiable for free now but is supported in the design flow. The > tools is avaible from Avertec (www.avertec.com) > > So there is no Timing Analysis tool included in the Alaince > tool set, correct ? So that makes the Alaince tools "very > limited" to say it in a nice way ... > > Just because the Alaince tools support a commercial tool does > not make them complete or useful. I can use Synopsys Design > compiler as part of a Cadance or Mentor design flow ... The alliance tools are there , you don't have to use them or like them or anything to do with them even remotely ok Peace :) > > > Lest you think I am all negative on the subject, some tools that I > > think are production ready tools are CVer (Verilog simulator), > > Dinotrace (waveform viewer) and Verilator (Verilog-to-C translator). > > Regards, > rudi > ======================================================== > ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: > ..............::: FPGAs * Full Custom ICs * IP Cores ::: > FREE IP Cores -> http://www.asics.ws/ > > _______________________________________________ > http://www.opencores.org/mailman/listinfo/cores _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

Quick Start on Opensource ASIC design VLSI Tools by Unknown on May 16, 2004			Not available!
Hello, I've been reading with great interest this ongoing discussion about the desirability of an end-to-end design flow for chips. The reason such tools don't exist as of now is very simple: It hasn't been worth any knowledgable engineer's while to write them, the ASIC and FPGA companies realize they can make money by charging for their tools, and the universities don't find that area of work interesting or worthwhile. So please allow me to call your bluff: How much are you willing to pay for a decent set of synthesis tools? I will grant that $100K+/seat which Cadence, Synopsys, Mentor, and so on want is TFM. On the other hand, it's clear that people are not lining up at the door to do the job for free. To catalyze development, the possibility of making money is required. What is an order-of-magnitude figure for what you would be willing to pay for an end-to-end, open-source flow with basic functionality? Stuart [q] All: A couple of things pop out of this discussion: 1) A complete -and free - backend solution is of great interest to all of us. 2) Alliance may be the closest thing we have (I haven't seen better alternatives proposed). How much work is it to build a useful timing tool? A primitive approach using verification suites and netlists with gate timing files and average wire load models should be pretty easy to put together. The kind of thing one gets out of DC - using netlist data only, does not seem (at least to me) as difficult a problem to solve as some that have already been solved. I guess it would be nice to have a free primetime or einstimer -- but for a lot of purposes, a somewhat less precise (and so more conservative) approach might be sufficient. Any thoughts from any of you that know more about this stuff??? bj[/q] Hello, I've been reading with great interest this ongoing discussion about the desirability of an end-to-end design flow for chips. The reason such tools don't exist as of now is very simple: It hasn't been worth any knowledgable engineer's while to write them, the ASIC and FPGA companies realize they can make money by charging for their tools, and the universities don't find that area of work interesting or worthwhile. So please allow me to call your bluff: How much are you willing to pay for a decent set of synthesis tools? I will grant that $100K+/seat which Cadence, Synopsys, Mentor, and so on want is TFM. On the other hand, it's clear that people are not lining up at the door to do the job for free. To catalyze development, the possibility of making money is required. What is an order-of-magnitude figure for what you would be willing to pay for an end-to-end, open-source flow with basic functionality? Stuart All: A couple of things pop out of this discussion: 1) A complete -and free - backend solution is of great interest to all of us. 2) Alliance may be the closest thing we have (I haven't seen better alternatives proposed). How much work is it to build a useful timing tool? A primitive approach using verification suites and netlists with gate timing files and average wire load models should be pretty easy to put together. The kind of thing one gets out of DC - using netlist data only, does not seem (at least to me) as difficult a problem to solve as some that have already been solved. I guess it would be nice to have a free primetime or einstimer -- but for a lot of purposes, a somewhat less precise (and so more conservative) approach might be sufficient. Any thoughts from any of you that know more about this stuff??? bj

Quick Start on Opensource ASIC design VLSI Tools by Unknown on May 17, 2004			Not available!
Aloha! bporcella wrote: [q] I guess it would be nice to have a free primetime or einstimer -- but for a lot of purposes, a somewhat less precise (and so more conservative) approach might be sufficient.[/q] As long as the "less precise" == more conservative, yes. Normally I would trade (1) speed and (2) scalability any day for precision in my STA-tool. -- Med vÃ¤nlig hÃ¤lsning, Yours Joachim StrÃ¶mbergson - Alltid i harmonisk svÃ¤ngning. VP, Research & Development ---------------------------------------------------------------------- InformAsic AB / Hugo Grauers gata 5B / SE-411 33 GÃ–TEBORG / Sweden Tel: +46 31 68 54 90 Fax: +46 31 68 54 91 Mobile: +46 733 75 97 02 E-mail: <A HREF="http://www.opencores.org/mailman/listinfo/cores">joachim.strombergson at informasic.com</A> Home: www.informasic.com ---------------------------------------------------------------------- Aloha! bporcella wrote: I guess it would be nice to have a free primetime or einstimer -- but for a lot of purposes, a somewhat less precise (and so more conservative) approach might be sufficient. As long as the "less precise" == more conservative, yes. Normally I would trade (1) speed and (2) scalability any day for precision in my STA-tool. -- Med vÃ¤nlig hÃ¤lsning, Yours Joachim StrÃ¶mbergson - Alltid i harmonisk svÃ¤ngning. VP, Research & Development ---------------------------------------------------------------------- InformAsic AB / Hugo Grauers gata 5B / SE-411 33 GÃ–TEBORG / Sweden Tel: +46 31 68 54 90 Fax: +46 31 68 54 91 Mobile: +46 733 75 97 02 E-mail: joachim.strombergson at informasic.com Home: www.informasic.com ----------------------------------------------------------------------

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