On Monday 17 May 2004 06:59 pm, you wrote:
Hi Phil, I haven't updated the core in awhile, but lately I've been considering what it would take to write a compiler for RCA. (I don't even know what the input language would be.) The only examples I have are hand drawn. I would recommend sitting down with some graph paper to sketch out a few -- I've found this to be an enlightening experience in architecture design. The architecture is fairily basic, so it's easy to get started. Each tile has a 3:1 LUT and a state register for each direction (north, south, west, and east) for a total of 4 LUTs and states regs per tile. The mulitplexers and the LUT functions are programmable. For example, an adder could look like this (Xs are tiles): These are the inputs: a3 --> X X X X c_out | X --> x4 X --> x3 X --> x2 X --> x0 Due to the unit delays between tiles, the input data need to be skewed accordingly. The state register is commonly used for de-skewing the pipeline during data routing. -- Tom Hawkins Launchbird Design Systems, Inc. Home of the Confluence Logic Design Language http://www.launchbird.com/