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wb_dma
by Unknown on Jun 1, 2004 |
Not available! | ||
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Hello , I'm an italian student, Davide, who is testing the wb_dma verilog code
for a thesis on NoC.I use the latest version of Modelsim to simulate the core , but the compiler returns many bugs in some files. In particular, it reports the lack of declaration of some macro and synthax errors. Can you help me?. Best regards Davide. |
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wb_dma
by Unknown on Jun 2, 2004 |
Not available! | ||
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On Tue, 2004-06-01 at 19:28, davciri at libero.it wrote:
Hello , I'm an italian student, Davide, who is testing the wb_dma verilog code
By default I do not support modelsim, as it has to many
wired "features". However if you would post the actual
errors you are getting, I'm sure somebody can help.
"Normal" verilog simulators seem to simulate the core
without any incidents. Try the free "CVER" verilog
simulator ... (see my web page -> fre tools for a link).
rudi
========================================================
ASICS.ws ::: Solutions for your ASIC/FPGA needs :::
..............::: FPGAs * Full Custom ICs * IP Cores :::
FREE IP Cores -> http://www.asics.ws/
for a thesis on NoC.I use the latest version of Modelsim to simulate the core , but the compiler returns many bugs in some files. In particular, it reports the lack of declaration of some macro and synthax errors. Can you help me?. Best regards Davide. |
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wb_dma
by pravakta on Aug 2, 2007 |
pravakta
Posts: 1 Joined: Jul 31, 2007 Last seen: Dec 5, 2015 |
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hi,
Can you please tell me the diffrence between software DMA request
and HARDware DMA request?plz..
----- Original Message -----
From: Rudolf Usselmannrudi at a...>
To:
Date: Wed Jun 2 13:01:19 CEST 2004
Subject: [oc] wb_dma
On Tue, 2004-06-01 at 19:28, davciri at l... wrote:
> Hello , I'm an italian student, Davide, who is testing the
wb_dma verilog code
> for a thesis on NoC.I use the latest version of Modelsim to
simulate the core ,
> but the compiler returns many bugs in some files. In
particular, it reports the
> lack of declaration of some macro and synthax errors.
> Can you help me?. > > Best regards > Davide. By default I do not support modelsim, as it has to many wired "features". However if you would post the actual errors you are getting, I'm sure somebody can help. "Normal" verilog simulators seem to simulate the core without any incidents. Try the free "CVER" verilog simulator ... (see my web page -> fre tools for a link). rudi ====================================================== ==
ASICS.ws ::: Solutions for your ASIC/FPGA needs :::
..............::: FPGAs * Full Custom ICs * IP Cores :::
FREE IP Cores -> http://www.asics.ws/
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