Hi,

I'm having fun coming up with a design for circuit similar to a Digital
Phase Locked Loop (DPLL). Unfortunately, my original design worked but
had issues and my new designs are getting more and more complicated.
I'm thinking I'm going down the wrong route so was looking for pointers
in the right direction (I can't find what I want on google etc).

The Problem:

Input: Square wave signal of a generally fixed frequency (though it may
start and stop) in the range 0.001Hz to 10MHz (quite a range!).

Output Required: Digital ramp or saw tooth waveform 48 bits wide which
is synchronised to the input signal updated at 25MHz. (This signal will
then be fed into a Cordic processor to produce a sinewave also
synchronised to the input signal.)

Locktime: 2 input clock cycles + 1uS.

Implementation: Within a Altera Cyclone EP1C20 running at 50MHz. No
external circuitry allowed.

I've looked at standard PLL and DPLL designs (such as fractional N) but
these all use analogue VCOs and wont operate over the frequency range
I need. I've considered designing an all digital VCO to emulate this
circuitry but this is A complicated and B won't meet my required lock
time.

My working design counted the period of the input signal, used serial
division to produce the reciprical of this and then used an accumilator to
produce the ramp. Some additional control circuitry was then used to
keep everything in synchronisation. Unfortunately, this control either
paused the accumilator or reset it to zero which adds unwanted
frequency artifacts. What I need is complete ramps which are either
lengthened or shortened to keep the synchronisation. This unfortunately
is getting complicated but I keep on trying...

Anybody have any better ideas?

Cheers,

Colin

Hello Colin! colin.opencores at scitec.uk.com wrote:


I don't know that my idea will be better, but I will try to help.
If you have that (impossible?) lock range requirements, why you don't
use some clock arbitration, with range detection.
In this case you must build some algorithm for handling this clock and
"prepare" DPLL for it... DPLL probably will
have smaller lock range in this case.
This principle is used in almost all situations where we need to
synchronize some signal to wide range of different
sync frequencies... and (D)PLL will have same (and smaller) lock range,
than input frequencies.

Hope this help.

Best regards,
-boggy

colin.opencores at scitec.uk.com wrote:
definitely has to be Altera here?
might be a case where the (Xilinx-style?) DLL might be or more relevance
than
(Altera current?) PLL's. This might be a place where more clock jitter
is agood thing.

otherwise, you need to build bit wide synchronisers that decide what to
do with
accumulators, I suspect.