I am developing a fully synthesizable 32 bit FIFO with programmable depth in verilog. AMBA APB compliance features have also been added to the design. I have completed the RTL and the functional verification. I need assistance w.r.t synthesizing the core ( both FPGA and ASIC will do ). Assistance will be greatly appreciated. Thanks and regards Unmesh unmesh at spikeindia.com -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20040616/cf577e3d/attachment.htm

that could be tricky.
Depends on whether it is synchronous or fallthrough,
how big it is. and what the test methodology is.

In fpga - most people forget test.
This is not a good idea in asic or full custom.
If its smaller than (say) 1K ff's, and synchronous, then fully
synthesized flops is
often the best solution. Maybe full scan for test.
If its fall thru - you really want a custom layout. You are in for a
world of hurt if you pass
that logic to many place and route tools. For me, custom layout and
synthesis do not sit well together.

Bigger than ~1K - you probably want a hard memory - which does not
synthesize well.
And you get the usual set of memory test issues, probably memory bist.

These are very different solutions. I'd sugggest a small soluton , and a
maybe big one.
john



Unmesh wrote:

Hi, I am currently learning hardware design. I wonder what is fallthrough. Thanks Chin-Khai Tang ----- Original Message ----- From: John Sheahanjrsheahan at o...> To: Date: Wed Jun 16 12:12:48 CEST 2004 Subject: [oc] Synthesis assistance required

memories tend to ba asynchronous or synchronous. A fall-through fifo is asynchronous, a write to the input will be available at the read port a short time later. No clocks needed. Used to be the standard fifo type. john wuwoze at yahoo.com wrote:

Memories are always tricky as has been pointed out. I've been designing chips and FPGAs for years and they always offer a challenge. In general before you can really do the design you need to understand the underlying memories available to you in your target technology. This is key. Although every company i work at tries to create generic memory types, FIFO, 1 port, 2 port, sync/async read/write ... some combinations don't work with a vendor or FPGA library due to the underlying memories. Why not just use flops? Way too big and a routing nightmare. This is even a greater problem in FPGAs. So is your design actually implementable in an FPGA/ASIC? Probably not since you can't truely parameterize a memory, since the underlying cell/macro size is fixed. You can paramterize the logic around the macro, but not the memory macro itself. The general flow is RTL -> (synthesizer) -> netlist -> (fitter/P&R) -> implemented design. For people learning now, it is much better since there are many free tools and the FPGAs offer a cheap implementation target to practice with. I would 1) get a synthesizer somehow. 2) i would target an FPGA, get the free software, read the docs, and build your core to use their underlying memories. 3) next synthesize using their directions, fit to the device, read the timing reports, etc etc till you get a design that really works. aka meets timing, uses a reasonable amount of logic, etc It sounds like you have done a good job on the front end. Now work on the back-end. This is critical. A design that doesn't meet timing is not a design. A design that uses a large flop array instead of a memory macro is not a design. They are science experiments. Actually i wish i only had to due science experiments :) --Mike ----- Original Message ----- From: Unmeshunmesh at s...> To: Date: Wed Jun 16 11:20:05 CEST 2004 Subject: [oc] Synthesis assistance required