We have recently designed a Spartan3 based board with this FPGA config scheme.
We have been trying to get this to work and we have not had much success so far.

We have put down the exact SiLabs based circuit, with a 16Mbit Flash. We can either use JTAG, platform PROMs or your FPGA config system on our board. We have already confirmed that JTAG and platform PROM methods work, and this has proved our board and Xilinx are working. The PROMs have now been removed and the Xilinx moved over to slave serial mode.
Using the SiLabs GUI etc we can easily work with the 8051, and we can program the flash, step through code etc.

The problem we have is that when we try and program the Xilinx the DONE line never transitions HIGH at the end, and the INIT_B line never goes LOW either.
We have tried some things including extra clocks at the end of the sequence, and we have checked that the data is MSB first by looking at it on an LA. In fact we see a correct starting procedure with PROG_B toggling, followed by INIT_B going HIGH. I have checked signal integrity and that timings are not violated (CCLK is around 12MHz).

The one area I am unsure about is whether the Xilinx IMPACT tool has to be setup in a special way? i.e. startup CCLK or other options?

The documentation for this project suggests a .bit file, and talks about it being a raw binary file, but actually it also has a header at the top. We also tried a .bin file which starts 0xFFFF (i.e. no header) but this didn't work either.

Has anyone used this system successfully with a Spartan3 and a FLASH?

Thanks
Marc

Fixed.

Ensure the startup clock is set to CCLK in the generate programming file options. Ours had somehow changed.

Marc