Hi,

The cores section was the only one I thought my question might fit. I hope so. Anyway, I'm pretty new to fpga's. But I'm wanting to use one for IO on a robot. I got a Cyclone II Starter Board from Altera and am using Quartus II 7.2 web edition. I've been able to knock out rs232 coms with a PC, making a hobby servo move around, control bigger motors, get a digital compass to work as well as a few other things. I've been working on IR ranging using an old Sharp GP2DO2 for a couple weeks now and having trouble.

The Sharp part has an input where it looks for specific timing to begin it's detection and then also send an 8 bit number out another line representing distance to object. You start with 2ms Hi followed by 70ms low followed by 8 cycles (the 8 bit distance) of 0.2ms Hi and 0.2ms Low. You read the bit during the 0.2ms Low. Pretty simple I thought.

Here's the problem. It seems no matter how I try to "wait" for 2ms and 70ms I get a compile error.

Error (10106): Verilog HDL Loop error at RangePulser.v(46): loop must terminate within 5000 iterations

I tried a for loop, a bunch of for loops, case loops, while loops. I was first dividing a 24mhz clock into 0.1ms ticks. For that I needed to loop 70000 times. So I made multiple iterations of short loops (
I know how state machines work but I'm clueless on using the interface for that type of file in Quartus. I also can't seem to get a waveform file going correctly.

Sorry for the wall of text. Wanted to give as much info as I could.

Thanks for any pointers in the right direction.

Chris

To create 1ms steps create a counter.
When the counter runs over the carry-out is your 1ms clock enable.


signal count : std_logic_vector (WIDTH downto 0);
signal count_reg : std_logic_vector (WIDTH -1 downto 0);
signal one_ms : std_logic;
...

begin

count one_ms
process (clk, rst)
begin
if (rst == '1') then
count_reg '0');
else
count_reg end if;
end process;


Enjoy,
Richard

To create 1ms steps create a counter.
When the counter runs over the carry-out is your 1ms clock enable.


signal count : std_logic_vector (WIDTH downto 0);
signal count_reg : std_logic_vector (WIDTH -1 downto 0);
signal one_ms : std_logic;
...

begin

count one_ms
process (clk, rst)
begin
if (rst == '1') then
count_reg '0');
else
count_reg end if;
end process;


Enjoy,
Richard

I think you have to create a counter with 1KHz frequency (1ms period) and use it as a base counter to create any time intervals you want by counting the pulses coming out from its output. A counter for 1KHz for 24MHz crystal on your board will be something like that in VHDL:

------------------------------------
process(clk) begin
if rising_edge(clk) then
if counter = 12 then
clk_1KHz counter else
counter end if;
end if;
end process;
------------------------------------

Oh man, I can't believe I didn't think of that. Especially having used a counter in a similar way. I guess nothing beats experience.

Thanks so much.

Chris

hi,

regarding simulation i suggest u to download 8.1 modelsim-altera web edition which is free of
license. easy to use and u can write testbenches instead of waveform file............

Or in the spirit of OpenCores use IcarusVerilog, which is free and open source!

ATB

--
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Cell: +44 (7970) 676050
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The code commented here is VHDL, does IvarusVerilog simulate it?

Regards,

Víctor

Hi Victor,

You are quite right - I'd missed that the example code was VHDL :-(. Icarus Verilog only takes Verilog as a source language. As far as I know there are no plans to extend it to VHDL.

I know of no open source VHDL simulator. The nearest you would get are a number of tools which can translate VHDL into Verilog, and then using Icarus Verilog. However all such translators have issues, so it is not really a satisfactory solution.

ATB,

Jeremy