Hello,

i need to know how could i realize an extrapolation in HW. i'll have 3 fixed point values stored in a RAM and normally i could get their linear equation and make the extrapolation handwritten ... but i don't know how to make it in HW ... so any ideas?!!

Thank you and best Regards,
Soha

Have you ever used any FPGA chip before? Do you have any experience in VHDL/Verilog?

You must perform a division for the extrapolation (is this correct?), this is the tricky part I think, since additions and substractions are easy implemented in modern synthesizers. You will have to design a divider or perform the division with a shifter unit. You will also have to design an Finite State Machine for the implementation of the loop that you will need, or if you have only 3 points maybe you can skip that and all the desing can be
Which FPGA device are you going to use? If you tell me, maybe I can give you more information.

thank you fro your reply ...
actually for my system, i'll be working on Stratix IV ... it'll be the first time (almost) to work on FPGA.

Till now, i've got a linear relation for the extrapolation that guided me to multiply by constant, so i guess it'll be an easy way by shifting and addition. (i got the equation by solving at special point which is x = 0 and x2-x1 = 1)

the equation i got is : Y = 0.5 (3y1 -y2) == 0.5 (4 y1 - y1 -y2) so i guess i'll be making it by :
1- 2 shifts left (4*y1)
2- substraction of y1 and y2
3- shift right to divide by 2.

Thank you for providing me with any other suggestions ..

thank you and best regards,
Soha

So only the Y1 and Y2 values will be variables? Your operation can be a single line in VHDL:

Y
Of course you must be careful in the declaration of your signals (signed/unsigned or whatever you want them to be).

and what will be the signal definition if i'm working on signed fixed point signals using VERILOG (14 bits signal, where 11 bits for the fractional part), you know in Verilog i just have the > operators to shift left and right and the vacant place will be filled by zero ..

thank you in advance!
Soha

Unfortunately I dont have enough experience in Verilog to help you. I work with VHDL.

thank you for your help, i really appreciate it

Soha