OpenCores

OpenCores

no use

no use

1/1

no use

no use

C16 processor by Unknown on Jul 11, 2004			Not available!
Hi, I'm having trouble getting the C16 processor to function correctly? I am trying to use it with a Digilent board with a Spartan IIe XC2S300E and Xilinx tools version 6.2.03i. The code required modification to port it to this board and it simulates fine with Modelsim but when the code executes it ignores even simple instructions such as JUMP. The program counter just keeps incrementing. I can see that the instructions are in memory OK. Its as if the Xilinx tools are not synthesizing the VHDL correctly. Any hints will be welcome. thanks Kevin Hi, I'm having trouble getting the C16 processor to function correctly? I am trying to use it with a Digilent board with a Spartan IIe XC2S300E and Xilinx tools version 6.2.03i. The code required modification to port it to this board and it simulates fine with Modelsim but when the code executes it ignores even simple instructions such as JUMP. The program counter just keeps incrementing. I can see that the instructions are in memory OK. Its as if the Xilinx tools are not synthesizing the VHDL correctly. Any hints will be welcome. thanks Kevin

C16 processor by arniml on Jul 11, 2004			arniml Posts: 4 Joined: Mar 22, 2004 Last seen: Jan 31, 2023
Hi Kevin! [q] I can see that the instructions are in memory OK. Its as if the Xilinx tools are not synthesizing the VHDL correctly. Any hints will be welcome. [/q] Have you considered to simulate the post place & route design? ISE can write a VHDL netlist of the design after P&R and simulating it should show the same problem. I never tried this with Modelsim, maybe you have to compile some Xilinx-specific libraries. Good luck! Arnim Hi Kevin! I can see that the instructions are in memory OK. Its as if the Xilinx tools are not synthesizing the VHDL correctly. Any hints will be welcome. Have you considered to simulate the post place & route design? ISE can write a VHDL netlist of the design after P&R and simulating it should show the same problem. I never tried this with Modelsim, maybe you have to compile some Xilinx-specific libraries. Good luck! Arnim

C16 processor by Unknown on Jul 12, 2004			Not available!
Arnim, Yes - you're right. It fails with the post-place and route simulation. I hadn't done that because somebody else said it was difficult to do with Modelsim... I wonder what causes the behavioural simulation to work but the post- place one to fail? thanks kevin ----- Original Message ----- From: <A HREF="http://www.opencores.org/mailman/listinfo/cores">arniml at o...</A><<A HREF="http://www.opencores.org/mailman/listinfo/cores">arniml at o...</A>> To: Date: Sun Jul 11 22:28:11 CEST 2004 Subject: [oc] C16 processor [q] Hi Kevin! [q]> I can see that the instructions are in memory OK. Its > as if the Xilinx tools are not synthesizing the VHDL [/q] correctly. [q]> Any hints will be welcome. [/q] Have you considered to simulate the post place & route design? ISE can write a VHDL netlist of the design after P&R and simulating it should show the same problem. I never tried this with Modelsim, maybe you have to compile some Xilinx-specific libraries. Good luck! Arnim [/q] Arnim, Yes - you're right. It fails with the post-place and route simulation. I hadn't done that because somebody else said it was difficult to do with Modelsim... I wonder what causes the behavioural simulation to work but the post- place one to fail? thanks kevin ----- Original Message ----- From: arniml at o...arniml at o...> To: Date: Sun Jul 11 22:28:11 CEST 2004 Subject: [oc] C16 processor Hi Kevin! > I can see that the instructions are in memory OK. Its > as if the Xilinx tools are not synthesizing the VHDL correctly. > Any hints will be welcome. Have you considered to simulate the post place & route design? ISE can write a VHDL netlist of the design after P&R and simulating it should show the same problem. I never tried this with Modelsim, maybe you have to compile some Xilinx-specific libraries. Good luck! Arnim

C16 processor by Unknown on Jul 12, 2004			Not available!
The behavioral simulation assumes that all state transitions are instantaneous. A successful behavioral simulation means your design COULD work. The timing simulation (post place and route) incorporates gate delays, routing delays, and other timing factors. Many models that work fine in behavioral simulations fail miserably when real-life signal timing is simulated. That is what makes it "hard to do." Usually, by reducing the clock rate, you can get the signals stabilized between clock cycles so the design will work correctly. You may also have to re-arrange your logic so that routing paths are shorter or operations do not use signals until they have stabilized. Steve On Sun, 2004-07-11 at 17:55, <A HREF="http://www.opencores.org/mailman/listinfo/cores">kevinjwhite at comcast.net</A> wrote: [q] Arnim, Yes - you're right. It fails with the post-place and route simulation. I hadn't done that because somebody else said it was difficult to do with Modelsim... I wonder what causes the behavioural simulation to work but the post- place one to fail? thanks kevin ----- Original Message ----- From: <A HREF="http://www.opencores.org/mailman/listinfo/cores">arniml at o...</A><<A HREF="http://www.opencores.org/mailman/listinfo/cores">arniml at o...</A>> To: Date: Sun Jul 11 22:28:11 CEST 2004 Subject: [oc] C16 processor [q]> Hi Kevin! > [q] > I can see that the instructions are in memory OK. Its > as if the Xilinx tools are not synthesizing the VHDL [/q] > correctly. [q] > Any hints will be welcome. [/q] > Have you considered to simulate the post place & route design? > ISE can > write a VHDL netlist of the design after P&R and simulating it > should > show the same problem. I never tried this with Modelsim, maybe you > have to compile some Xilinx-specific libraries. > Good luck! > Arnim > > [/q] _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A>[/q] -- Steven R. McQueen McQueen Technologies, Inc. (909) 809-3232 <A HREF="http://www.opencores.org/mailman/listinfo/cores">srmcqueen at mcqueentech.com</A> The behavioral simulation assumes that all state transitions are instantaneous. A successful behavioral simulation means your design COULD work. The timing simulation (post place and route) incorporates gate delays, routing delays, and other timing factors. Many models that work fine in behavioral simulations fail miserably when real-life signal timing is simulated. That is what makes it "hard to do." Usually, by reducing the clock rate, you can get the signals stabilized between clock cycles so the design will work correctly. You may also have to re-arrange your logic so that routing paths are shorter or operations do not use signals until they have stabilized. Steve On Sun, 2004-07-11 at 17:55, kevinjwhite at comcast.net wrote: Arnim, Yes - you're right. It fails with the post-place and route simulation. I hadn't done that because somebody else said it was difficult to do with Modelsim... I wonder what causes the behavioural simulation to work but the post- place one to fail? thanks kevin ----- Original Message ----- From: arniml at o...arniml at o...> To: Date: Sun Jul 11 22:28:11 CEST 2004 Subject: [oc] C16 processor > Hi Kevin! > > I can see that the instructions are in memory OK. Its > as if the Xilinx tools are not synthesizing the VHDL > correctly. > Any hints will be welcome. > Have you considered to simulate the post place & route design? > ISE can > write a VHDL netlist of the design after P&R and simulating it > should > show the same problem. I never tried this with Modelsim, maybe you > have to compile some Xilinx-specific libraries. > Good luck! > Arnim > > _______________________________________________ http://www.opencores.org/mailman/listinfo/cores -- Steven R. McQueen McQueen Technologies, Inc. (909) 809-3232 srmcqueen at mcqueentech.com

C16 processor by Unknown on Jul 12, 2004			Not available!
Steven, The problem also occurs with just the post-translation simulation (not just post-Palce and route). Does post translation simulation include timing simulation? I think it doesn't. The problem is not dependent on clock rate (it fails even while single stepping at 1Hz in the FPGA). As far as I understand the logic it looks pure synchronous. - so it would seem that the most likely scenario is that the new Xilinx tools interpret the code differently from the simulation. Since it originally worked with XST version 5 (the files in CVS on Opencores include a version 5 project file) it would seem that the Xilinx tools have changed. thanks kevin ----- Original Message ----- From: Steven R. McQueen<<A HREF="http://www.opencores.org/mailman/listinfo/cores">srmcqueen at m...</A>> To: Date: Mon Jul 12 05:45:32 CEST 2004 Subject: [oc] C16 processor [q] The behavioral simulation assumes that all state transitions are instantaneous. A successful behavioral simulation means your design COULD work. The timing simulation (post place and route) incorporates gate delays, routing delays, and other timing factors. Many models that work fine in behavioral simulations fail miserably when real-life signal timing is simulated. That is what makes it "hard to do." Usually, by reducing the clock rate, you can get the signals stabilized between clock cycles so the design will work correctly. You may also have to re-arrange your logic so that routing paths are shorter or operations do not use signals until they have stabilized. Steve On Sun, 2004-07-11 at 17:55, <A HREF="http://www.opencores.org/mailman/listinfo/cores">kevinjwhite at c...</A> wrote: [q]> Arnim, > > Yes - you're right. It fails with the post-place and route [/q] simulation. I [q]> hadn't done that because somebody else said it was difficult [/q] to do with [q]> Modelsim... > > I wonder what causes the behavioural simulation to work but [/q] the post- [q]> place one to fail? > > thanks > > kevin > > ----- Original Message ----- > From: <A HREF="http://www.opencores.org/mailman/listinfo/cores">arniml at o...</A><<A HREF="http://www.opencores.org/mailman/listinfo/cores">arniml at o...</A>> > To: > Date: Sun Jul 11 22:28:11 CEST 2004 > Subject: [oc] C16 processor > [q] > Hi Kevin! > [q]> > I can see that the instructions are in memory OK. [/q] Its [q]> > as if the Xilinx tools are not synthesizing the VHDL [/q] > correctly. [q]> > Any hints will be welcome. [/q] > Have you considered to simulate the post place & [/q] route design? [q] > ISE can > write a VHDL netlist of the design after P&R and [/q] simulating it [q] > should > show the same problem. I never tried this with Modelsim, [/q] maybe you [q] > have to compile some Xilinx-specific libraries. > Good luck! > Arnim > > [/q] > _______________________________________________ > <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> [/q] -- Steven R. McQueen McQueen Technologies, Inc. (909) 809-3232 <A HREF="http://www.opencores.org/mailman/listinfo/cores">srmcqueen at m...</A> [/q] Steven, The problem also occurs with just the post-translation simulation (not just post-Palce and route). Does post translation simulation include timing simulation? I think it doesn't. The problem is not dependent on clock rate (it fails even while single stepping at 1Hz in the FPGA). As far as I understand the logic it looks pure synchronous. - so it would seem that the most likely scenario is that the new Xilinx tools interpret the code differently from the simulation. Since it originally worked with XST version 5 (the files in CVS on Opencores include a version 5 project file) it would seem that the Xilinx tools have changed. thanks kevin ----- Original Message ----- From: Steven R. McQueensrmcqueen at m...> To: Date: Mon Jul 12 05:45:32 CEST 2004 Subject: [oc] C16 processor The behavioral simulation assumes that all state transitions are instantaneous. A successful behavioral simulation means your design COULD work. The timing simulation (post place and route) incorporates gate delays, routing delays, and other timing factors. Many models that work fine in behavioral simulations fail miserably when real-life signal timing is simulated. That is what makes it "hard to do." Usually, by reducing the clock rate, you can get the signals stabilized between clock cycles so the design will work correctly. You may also have to re-arrange your logic so that routing paths are shorter or operations do not use signals until they have stabilized. Steve On Sun, 2004-07-11 at 17:55, kevinjwhite at c... wrote: > Arnim, > > Yes - you're right. It fails with the post-place and route simulation. I > hadn't done that because somebody else said it was difficult to do with > Modelsim... > > I wonder what causes the behavioural simulation to work but the post- > place one to fail? > > thanks > > kevin > > ----- Original Message ----- > From: arniml at o...arniml at o...> > To: > Date: Sun Jul 11 22:28:11 CEST 2004 > Subject: [oc] C16 processor > > Hi Kevin! > > > I can see that the instructions are in memory OK. Its > > as if the Xilinx tools are not synthesizing the VHDL > correctly. > > Any hints will be welcome. > Have you considered to simulate the post place & route design? > ISE can > write a VHDL netlist of the design after P&R and simulating it > should > show the same problem. I never tried this with Modelsim, maybe you > have to compile some Xilinx-specific libraries. > Good luck! > Arnim > > > _______________________________________________ > http://www.opencores.org/mailman/listinfo/cores -- Steven R. McQueen McQueen Technologies, Inc. (909) 809-3232 srmcqueen at m...

C16 processor by arniml on Jul 12, 2004			arniml Posts: 4 Joined: Mar 22, 2004 Last seen: Jan 31, 2023
Hi Kevin, [q] The problem also occurs with just the post-translation simulation (not just post-Palce and route). The problem is not dependent on clock rate (it fails even while single stepping at 1Hz in the FPGA). [/q] So we're not looking at a performance (setup) problem?! [q] so it would seem that the most likely scenario is that the new Xilinx tools interpret the code differently from the simulation.[/q] Probably yes. Can you make sure that a) all sensitivity lists are complete? b) signals carrying clocks are not assigned further to signals ("clock renaming")? c) the functionality of the netlist and the RTL VHDL are equivalent? a) and b) are likely to cause different behaviour of the RTL and gatelevel (synthesized/translated) designs. c) would discover compiler errors but requires a separate tool for formal verification. Cheers Arnim Hi Kevin, The problem also occurs with just the post-translation simulation (not just post-Palce and route). The problem is not dependent on clock rate (it fails even while single stepping at 1Hz in the FPGA). So we're not looking at a performance (setup) problem?! so it would seem that the most likely scenario is that the new Xilinx tools interpret the code differently from the simulation. Probably yes. Can you make sure that a) all sensitivity lists are complete? b) signals carrying clocks are not assigned further to signals ("clock renaming")? c) the functionality of the netlist and the RTL VHDL are equivalent? a) and b) are likely to cause different behaviour of the RTL and gatelevel (synthesized/translated) designs. c) would discover compiler errors but requires a separate tool for formal verification. Cheers Arnim

C16 processor by Unknown on Sep 2, 2004			Not available!
Hi [q]> The problem also occurs with just the post-translation simulation > (not just post-Palce and route). > The problem is not dependent on clock rate (it fails even while > single stepping at 1Hz in the FPGA).[/q] I'ts very possible that will be a bug with the XST syntesis. Â¿ What version of ISE are you using ?. I had similar problems with the T80 core and ISE 5.2, when i upgraded to ISE 6 the problems dissapear. Grettings Daniel Quintero Hi > The problem also occurs with just the post-translation simulation > (not just post-Palce and route). > The problem is not dependent on clock rate (it fails even while > single stepping at 1Hz in the FPGA). I'ts very possible that will be a bug with the XST syntesis. Â¿ What version of ISE are you using ?. I had similar problems with the T80 core and ISE 5.2, when i upgraded to ISE 6 the problems dissapear. Grettings Daniel Quintero

no use

no use

1/1

no use

no use

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.