OpenCores

OpenCores

Parallel Array Processor Project

First

Prev

2/5

Next

Last

Parallel Array Processor Project by markus on Aug 16, 2004			markus Posts: 32 Joined: Dec 9, 2002 Last seen: Apr 30, 2013
[q] There Is a complete body of knowledge relative to SIMD processing. <A HREF="http://www.cse.ogi.edu/~strom/papers/cnaps.pdf">http://www.cse.ogi.edu/~strom/papers/cnaps.pdf</A> [/q] Thanks for the link. [q] You certainly should understand the MMX extensions to the Pentium as a preliminary to building the kind of core you are talking about.[/q] Yes, I'm quite familiar with those. My interest, in fact, is not on the SIMD processing. It's hard, if not impossible, to build a general-purpose microprocessor based strictly on the SIMD-architecture without losing lot's of processing power. As a co-processor, they are just fine. My area of intrest is MIMD and I'm very aware, that the architecture I'm currently planning won't beat SIMD-processors or systolic arrays in their strong area. That's not a target for the project; the target is to design architecture and tools for general purpose parallel processor. The scalability is one of the key targets; no matter how many processors or GIPS you have in your desktop computer, it's not enough tomorrow ;-D [q] A word of caution. The application space for these machines is high performance digital filtering [...] beating the DSP's ( and the Pentium MMX for that matter) is not easy. [/q] I'm not going to even think about it. --- Offtopic: [q] (neural networks have not proved commercially viable).[/q] That's true. As a programmer, IMO the neural networks have a few critical lackness: ) The fundamental usage of NNs is transformation functions, which are too complex for _human_brains_ to be expressed in a formal language. But all these problems are still solvable with a conventional processors. ) They are not general purpose; some tasks are "neuralized" easier than others and some of the tasks are almost impossible to be executed by a general neural network processor (without any special hardware solutions). Just think, that not all tasks are easy to be expressed with multiply-accumulate-treshold -operations. ) Learning algorithms used to "program" the networks are currently capable of tune the NN for transformation functions - they can't resolve signal feedbacks in general case (there exist some special-case algorithms, e.g. for speech recognition). [I was once scetching a programming language for NNs and I studied them a lot ;-)] There Is a complete body of knowledge relative to SIMD processing. http://www.cse.ogi.edu/~strom/papers/cnaps.pdf Thanks for the link. You certainly should understand the MMX extensions to the Pentium as a preliminary to building the kind of core you are talking about. Yes, I'm quite familiar with those. My interest, in fact, is not on the SIMD processing. It's hard, if not impossible, to build a general-purpose microprocessor based strictly on the SIMD-architecture without losing lot's of processing power. As a co-processor, they are just fine. My area of intrest is MIMD and I'm very aware, that the architecture I'm currently planning won't beat SIMD-processors or systolic arrays in their strong area. That's not a target for the project; the target is to design architecture and tools for general purpose parallel processor. The scalability is one of the key targets; no matter how many processors or GIPS you have in your desktop computer, it's not enough tomorrow ;-D A word of caution. The application space for these machines is high performance digital filtering [...] beating the DSP's ( and the Pentium MMX for that matter) is not easy. I'm not going to even think about it. --- Offtopic: (neural networks have not proved commercially viable). That's true. As a programmer, IMO the neural networks have a few critical lackness: ) The fundamental usage of NNs is transformation functions, which are too complex for _human_brains_ to be expressed in a formal language. But all these problems are still solvable with a conventional processors. ) They are not general purpose; some tasks are "neuralized" easier than others and some of the tasks are almost impossible to be executed by a general neural network processor (without any special hardware solutions). Just think, that not all tasks are easy to be expressed with multiply-accumulate-treshold -operations. ) Learning algorithms used to "program" the networks are currently capable of tune the NN for transformation functions - they can't resolve signal feedbacks in general case (there exist some special-case algorithms, e.g. for speech recognition). [I was once scetching a programming language for NNs and I studied them a lot ;-)]

Parallel Array Processor Project by Unknown on Aug 16, 2004			Not available!
Aloha! <A HREF="http://www.opencores.org/mailman/listinfo/cores">markus at reaaliaika.net</A> wrote: [q] My area of intrest is MIMD and I'm very aware, that the architecture I'm currently planning won't beat SIMD-processors or systolic arrays in their strong area. That's not a target for the project; the target is to design architecture and tools for general purpose parallel processor. The scalability is one of the key targets; no matter how many processors or GIPS you have in your desktop computer, it's not enough tomorrow ;-D[/q] Yes and no, see footnote [1]. The problems I see with building massive MIMDs on anything (cabinet or chip) is program model and communication. And esp for the embedded/integrated thingy you don't want to have to resort to MPI for you interprocessor communication. AFAIK there have been some experiments done loading several tens of PicBlaze/KCPSMs onto an FPGA and have them work together to solve big tasks. The KCPSM is basically a programmable state-machine with a few instructions and a very limited amount of both program storage and data ram. For your neural network experiments, I believe that type of implementation should suffice. Implementing a perceptron should not take too many instructions. Ken Chapman have written a nice, five part article series on how design decisions and implementation of the processor: <A HREF="http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sTechX_ID=kc_emb_micro&languageID=1">http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sTechX_ID=kc_emb_micro&languageID=1</A> Also, since you are planning to use an FPGA as platform, check out GÃ¶ran Bilskis insights on efficient processor design on a prelaid architecture (the FPGA). These were posted about a week ago on the list (The "Why open processors are som much slower..."). There have been many attempts at creating multi-core-designs. One of them were BOPS, who had a scalable architecture for DSP-cores that you then could instanciate into your ASIC. Important features were specific communication devices that scaled in performance with the DSP-cores. Unfortunately BOPS have died. There are some stuff on the webb still, this article for example: <A HREF="http://www.elecdesign.com/Articles/Index.cfm?ArticleID=3496&pg=2">http://www.elecdesign.com/Articles/Index.cfm?ArticleID=3496&pg=2</A> [1] Unless the HW is unable to run the Windows OS, which is the perrenial compute hog. ;-) More seriously, thera are some very interesting grand challenges. Look at Vernor Vinges singularity ideas for the wild ones. But global weather prediction, gene/bio-design (not just analysis, but engineering of DNA-based stuff) as well as more down-to-earthy things like real-time speech recognition and synthesis. Fortunately, with nano-technology if some wild ideas are to go by, we should be able to get basically as much computing power as we are going to need EVER: <A HREF="http://www.aeiveos.com/~bradbury/MatrioshkaBrains/index.html">http://www.aeiveos.com/~bradbury/MatrioshkaBrains/index.html</A> -- Med vÃ¤nlig hÃ¤lsning, Yours Joachim StrÃ¶mbergson - Alltid i harmonisk svÃ¤ngning. VP, Research & Development ---------------------------------------------------------------------- InformAsic AB / Hugo Grauers gata 5B / SE-411 33 GÃ–TEBORG / Sweden Tel: +46 31 68 54 90 Fax: +46 31 68 54 91 Mobile: +46 733 75 97 02 E-mail: <A HREF="http://www.opencores.org/mailman/listinfo/cores">joachim.strombergson at informasic.com</A> Home: www.informasic.com ---------------------------------------------------------------------- Aloha! markus at reaaliaika.net wrote: My area of intrest is MIMD and I'm very aware, that the architecture I'm currently planning won't beat SIMD-processors or systolic arrays in their strong area. That's not a target for the project; the target is to design architecture and tools for general purpose parallel processor. The scalability is one of the key targets; no matter how many processors or GIPS you have in your desktop computer, it's not enough tomorrow ;-D Yes and no, see footnote [1]. The problems I see with building massive MIMDs on anything (cabinet or chip) is program model and communication. And esp for the embedded/integrated thingy you don't want to have to resort to MPI for you interprocessor communication. AFAIK there have been some experiments done loading several tens of PicBlaze/KCPSMs onto an FPGA and have them work together to solve big tasks. The KCPSM is basically a programmable state-machine with a few instructions and a very limited amount of both program storage and data ram. For your neural network experiments, I believe that type of implementation should suffice. Implementing a perceptron should not take too many instructions. Ken Chapman have written a nice, five part article series on how design decisions and implementation of the processor: http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sTechX_ID=kc_emb_micro&languageID=1 Also, since you are planning to use an FPGA as platform, check out GÃ¶ran Bilskis insights on efficient processor design on a prelaid architecture (the FPGA). These were posted about a week ago on the list (The "Why open processors are som much slower..."). There have been many attempts at creating multi-core-designs. One of them were BOPS, who had a scalable architecture for DSP-cores that you then could instanciate into your ASIC. Important features were specific communication devices that scaled in performance with the DSP-cores. Unfortunately BOPS have died. There are some stuff on the webb still, this article for example: http://www.elecdesign.com/Articles/Index.cfm?ArticleID=3496&pg=2 [1] Unless the HW is unable to run the Windows OS, which is the perrenial compute hog. ;-) More seriously, thera are some very interesting grand challenges. Look at Vernor Vinges singularity ideas for the wild ones. But global weather prediction, gene/bio-design (not just analysis, but engineering of DNA-based stuff) as well as more down-to-earthy things like real-time speech recognition and synthesis. Fortunately, with nano-technology if some wild ideas are to go by, we should be able to get basically as much computing power as we are going to need EVER: http://www.aeiveos.com/~bradbury/MatrioshkaBrains/index.html -- Med vÃ¤nlig hÃ¤lsning, Yours Joachim StrÃ¶mbergson - Alltid i harmonisk svÃ¤ngning. VP, Research & Development ---------------------------------------------------------------------- InformAsic AB / Hugo Grauers gata 5B / SE-411 33 GÃ–TEBORG / Sweden Tel: +46 31 68 54 90 Fax: +46 31 68 54 91 Mobile: +46 733 75 97 02 E-mail: joachim.strombergson at informasic.com Home: www.informasic.com ----------------------------------------------------------------------

Parallel Array Processor Project by Unknown on Aug 16, 2004			Not available!
Seems to me Douglas Adams was on the right path with "Deep Thought" The answer is 42 .... but what is the question ? What is the problem you are trying to solve with your parallel array ? The key seems to be to find a problem that a new technology solves. ie. what does my parallel array have to offer now that was not practical before. You might look to see if there is any work on computational density and heat distribution in chips. Parallel Processing Arrays should have the advantage of distributing heat dissipation, across the chip. You also have the advantage of localising high speed computational routing to small cells on the chip rather than routing data across the whole chip. To solve the distributed heat problem you need to look at how best to perform computational load balancing and the architecture of the parallel array best suited to implementing such a load balancing algorithm. Dilbert. Joachim StrÃ¶mbergson wrote: [q] Fortunately, with nano-technology if some wild ideas are to go by, we should be able to get basically as much computing power as we are going to need EVER: <A HREF="http://www.aeiveos.com/~bradbury/MatrioshkaBrains/index.html">http://www.aeiveos.com/~bradbury/MatrioshkaBrains/index.html</A> [/q] -- <A HREF="http://members.optushome.com.au/jekent">http://members.optushome.com.au/jekent</A> Seems to me Douglas Adams was on the right path with "Deep Thought" The answer is 42 .... but what is the question ? What is the problem you are trying to solve with your parallel array ? The key seems to be to find a problem that a new technology solves. ie. what does my parallel array have to offer now that was not practical before. You might look to see if there is any work on computational density and heat distribution in chips. Parallel Processing Arrays should have the advantage of distributing heat dissipation, across the chip. You also have the advantage of localising high speed computational routing to small cells on the chip rather than routing data across the whole chip. To solve the distributed heat problem you need to look at how best to perform computational load balancing and the architecture of the parallel array best suited to implementing such a load balancing algorithm. Dilbert. Joachim StrÃ¶mbergson wrote: Fortunately, with nano-technology if some wild ideas are to go by, we should be able to get basically as much computing power as we are going to need EVER: http://www.aeiveos.com/~bradbury/MatrioshkaBrains/index.html -- http://members.optushome.com.au/jekent

Parallel Array Processor Project by markus on Aug 16, 2004			markus Posts: 32 Joined: Dec 9, 2002 Last seen: Apr 30, 2013
[q] <A HREF="http://www.opencores.org/mailman/listinfo/cores">markus at r...</A> wrote: [q]> My area of intrest is MIMD and I'm very aware, that the > architecture I'm currently planning won't beat SIMD-processors > or systolic arrays in their strong area. That's not a target for > the project; the target is to design architecture and tools > for general purpose parallel processor. > [/q] [...] [q] The problems I see with building massive MIMDs on anything (cabinet or chip) is program model and communication.[/q] You're absolutely right here - the programming model is terrible. In the early 90's, when I was last time working on this project, I was convinced, that the difficultiness of programming makes the model unusable. And altought I now have over 10 years more experience of programming, including parallel systems, with a strong motivation for solving the thing, it's still hard and desperous mission. But, most of you are probably familiar with VHDL - that's one of the existing parallel languages and you probably know, that it's not impossible to make something usable with it, and it's even possible to make the code somewhat understandable, too. About the communication, it's a thing with which you just have to live, if you're designing massively parallel systems. [q] And esp for the embedded/integrated thingy you don't want to have to resort to MPI for you interprocessor communication. [/q] Maybe not. --- [PicBlaze/KCPSM] [q] For your neural network experiments, I believe that type of implementation should suffice. Implementing a perceptron should not take too many instructions. [/q] Certainly, but I'm not interested (any more / at the moment) on neural networks. They are fine in the area where they work, but as a general purpose computational model they need a lots of refinements for getting them work. The KCPSM model seemed interesting and I'll study it more. [q] Also, since you are planning to use an FPGA as platform,[/q] In fact, I'm not, but I think that FPGA would be one of the most easy way to test the hardware solutions... [q] check out GÃ¶ran Bilskis insights on efficient processor design on a prelaid architecture (the FPGA). These were posted about a week ago on the list (The "Why open processors are som much slower..."). [/q] OK, thanks. I already readed those, when they arrived to this list, but I'll check them again. I'm also following the discussion of the 8-bit microprocessors (Z80 and 8088 compatibles). [BOPS] [q] There have been many attempts at creating multi-core-designs.[/q] [...] [q] Unfortunately BOPS have died. There are some stuff on the webb still, this article for example: <A HREF="http://www.elecdesign.com/Articles/Index.cfm?ArticleID=3496&pg=2">http://www.elecdesign.com/Articles/Index.cfm?ArticleID=3496&pg=2</A> [/q] All right, thanks. --- And then to the interesting part ;-) [q]> The scalability is one of the key targets; no matter how many > processors or GIPS you have in your desktop computer, it's not > enough tomorrow ;-D [/q] Yes and no, see footnote [1]. [/q] [...] [q] [1] Unless the HW is unable to run the Windows OS, which is the perrenial compute hog. ;-)[/q] Certainly they port Windows for forthcoming processors, too - they already ported it for embedded devices ;-) [q] More seriously, thera are some very interesting grand challenges. Look at Vernor Vinges singularity ideas for the wild ones. But global weather prediction, gene/bio-design (not just analysis, but engineering of DNA-based stuff) as well as more down-to-earthy things like real-time speech recognition and synthesis.[/q] Yes, those are some application areas for parallel computing, but I think that we doesn't need to go that far. Each of our desktop computers have all the time several applications running and most of them are nowadays "threaded" - this has opened the door for SMP-computers, which were mostly unusable (i.e. the software couldn't use the performance) a decade ago. Even a "single-CPU" modern desktop computers have a parallel co- processor, the GPU, located in the graphics card - and they are becoming more and more programmable (see <A HREF="http://www.gpgpu.org">http://www.gpgpu.org</A>). And still, there's need for increasing the processing power to make better games, to support realtime raytracing and to support live video effects. Even the highest performance Pentium feels slow, if you for example make a noice reduction for your half hour video recording. [q] Fortunately, with nano-technology if some wild ideas are to go by, we should be able to get basically as much computing power as we are going to need EVER: <A HREF="http://www.aeiveos.com/~bradbury/MatrioshkaBrains/index.html">http://www.aeiveos.com/~bradbury/MatrioshkaBrains/index.html</A> [/q] Yes, here's the goal! ;-) But seriously, one can imagine computer systems like that, but how are they programmed? In which language? How are the processing cells constructed (instruction set, memories, external connections, etc)? What kind of memory bus those computers have? What kind of peripherals? markus at r... wrote: > My area of intrest is MIMD and I'm very aware, that the > architecture I'm currently planning won't beat SIMD-processors > or systolic arrays in their strong area. That's not a target for > the project; the target is to design architecture and tools > for general purpose parallel processor. > [...] The problems I see with building massive MIMDs on anything (cabinet or chip) is program model and communication. You're absolutely right here - the programming model is terrible. In the early 90's, when I was last time working on this project, I was convinced, that the difficultiness of programming makes the model unusable. And altought I now have over 10 years more experience of programming, including parallel systems, with a strong motivation for solving the thing, it's still hard and desperous mission. But, most of you are probably familiar with VHDL - that's one of the existing parallel languages and you probably know, that it's not impossible to make something usable with it, and it's even possible to make the code somewhat understandable, too. About the communication, it's a thing with which you just have to live, if you're designing massively parallel systems. And esp for the embedded/integrated thingy you don't want to have to resort to MPI for you interprocessor communication. Maybe not. --- [PicBlaze/KCPSM] For your neural network experiments, I believe that type of implementation should suffice. Implementing a perceptron should not take too many instructions. Certainly, but I'm not interested (any more / at the moment) on neural networks. They are fine in the area where they work, but as a general purpose computational model they need a lots of refinements for getting them work. The KCPSM model seemed interesting and I'll study it more. Also, since you are planning to use an FPGA as platform, In fact, I'm not, but I think that FPGA would be one of the most easy way to test the hardware solutions... check out GÃ¶ran Bilskis insights on efficient processor design on a prelaid architecture (the FPGA). These were posted about a week ago on the list (The "Why open processors are som much slower..."). OK, thanks. I already readed those, when they arrived to this list, but I'll check them again. I'm also following the discussion of the 8-bit microprocessors (Z80 and 8088 compatibles). [BOPS] There have been many attempts at creating multi-core-designs. [...] Unfortunately BOPS have died. There are some stuff on the webb still, this article for example: http://www.elecdesign.com/Articles/Index.cfm?ArticleID=3496&pg=2 All right, thanks. --- And then to the interesting part ;-) > The scalability is one of the key targets; no matter how many > processors or GIPS you have in your desktop computer, it's not > enough tomorrow ;-D Yes and no, see footnote [1]. [...] [1] Unless the HW is unable to run the Windows OS, which is the perrenial compute hog. ;-) Certainly they port Windows for forthcoming processors, too - they already ported it for embedded devices ;-) More seriously, thera are some very interesting grand challenges. Look at Vernor Vinges singularity ideas for the wild ones. But global weather prediction, gene/bio-design (not just analysis, but engineering of DNA-based stuff) as well as more down-to-earthy things like real-time speech recognition and synthesis. Yes, those are some application areas for parallel computing, but I think that we doesn't need to go that far. Each of our desktop computers have all the time several applications running and most of them are nowadays "threaded" - this has opened the door for SMP-computers, which were mostly unusable (i.e. the software couldn't use the performance) a decade ago. Even a "single-CPU" modern desktop computers have a parallel co- processor, the GPU, located in the graphics card - and they are becoming more and more programmable (see http://www.gpgpu.org). And still, there's need for increasing the processing power to make better games, to support realtime raytracing and to support live video effects. Even the highest performance Pentium feels slow, if you for example make a noice reduction for your half hour video recording. Fortunately, with nano-technology if some wild ideas are to go by, we should be able to get basically as much computing power as we are going to need EVER: http://www.aeiveos.com/~bradbury/MatrioshkaBrains/index.html Yes, here's the goal! ;-) But seriously, one can imagine computer systems like that, but how are they programmed? In which language? How are the processing cells constructed (instruction set, memories, external connections, etc)? What kind of memory bus those computers have? What kind of peripherals?

Parallel Array Processor Project by nico on Aug 16, 2004			nico Posts: 21 Joined: Jun 21, 2008 Last seen: May 11, 2009
[q] <A HREF="http://www.opencores.org/mailman/listinfo/cores">markus at r...</A> wrote: [q]> My area of intrest is MIMD and I'm very aware, that the > architecture I'm currently planning won't beat SIMD-processors > or systolic arrays in their strong area. That's not a target for > the project; the target is to design architecture and tools > for general purpose parallel processor. >[/q] [...] [q] The problems I see with building massive MIMDs on anything (cabinet or chip) is program model and communication.[/q] You're absolutely right here - the programming model is terrible. In the early 90's, when I was last time working on this project, I was convinced, that the difficultiness of programming makes the model unusable. And altought I now have over 10 years more experience of programming, including parallel systems, with a strong motivation for solving the thing, it's still hard and desperous mission. But, most of you are probably familiar with VHDL - that's one of the existing parallel languages and you probably know, that it's not impossible to make something usable with it, and it's even possible to make the code somewhat understandable, too. [/q] For a large scale small cpu array, VHDL could do a great job i beleive. [...] [q] Fortunately, with nano-technology if some wild ideas are to go by, we should be able to get basically as much computing power as we are going to need EVER: <A HREF="http://www.aeiveos.com/~bradbury/MatrioshkaBrains/index.html">http://www.aeiveos.com/~bradbury/MatrioshkaBrains/index.html</A>[/q] Yes, here's the goal! ;-) But seriously, one can imagine computer systems like that, but how are they programmed? In which language? How are the processing cells constructed (instruction set, memories, external connections, etc)? What kind of memory bus those computers have? What kind of peripherals?[/q] I think the best model is a PC cluster. Every node contain memory and is linked to the closest other cell. Then the routing algorithm could be fractal like. [q] _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> [/q] markus at r... wrote: > My area of intrest is MIMD and I'm very aware, that the > architecture I'm currently planning won't beat SIMD-processors > or systolic arrays in their strong area. That's not a target for > the project; the target is to design architecture and tools > for general purpose parallel processor. > [...] The problems I see with building massive MIMDs on anything (cabinet or chip) is program model and communication. You're absolutely right here - the programming model is terrible. In the early 90's, when I was last time working on this project, I was convinced, that the difficultiness of programming makes the model unusable. And altought I now have over 10 years more experience of programming, including parallel systems, with a strong motivation for solving the thing, it's still hard and desperous mission. But, most of you are probably familiar with VHDL - that's one of the existing parallel languages and you probably know, that it's not impossible to make something usable with it, and it's even possible to make the code somewhat understandable, too. For a large scale small cpu array, VHDL could do a great job i beleive. [...] Fortunately, with nano-technology if some wild ideas are to go by, we should be able to get basically as much computing power as we are going to need EVER: http://www.aeiveos.com/~bradbury/MatrioshkaBrains/index.html Yes, here's the goal! ;-) But seriously, one can imagine computer systems like that, but how are they programmed? In which language? How are the processing cells constructed (instruction set, memories, external connections, etc)? What kind of memory bus those computers have? What kind of peripherals? I think the best model is a PC cluster. Every node contain memory and is linked to the closest other cell. Then the routing algorithm could be fractal like. _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

Parallel Array Processor Project by markus on Aug 16, 2004			markus Posts: 32 Joined: Dec 9, 2002 Last seen: Apr 30, 2013
[q] Seems to me Douglas Adams was on the right path with "Deep Thought" The answer is 42 .... but what is the question ? [/q] ;-D [q] What is the problem you are trying to solve with your parallel array ? [/q] Hmmh, well... The objectiveness for the project are: 1) To construct a cell design, which, when connected together to form a regular pattern array, would form a general purpose parallel processor. 2) To construct programming tools (model, languages, OS) for programming those cells to co-operatively solve computational problems, like how to save your Word document to disk. I haven't ever thought this at the point of problem-solution view, so I have some difficultiness to form the objetiveness in that way. If I now think the path, which led to this construction again, I could probably try to form it like this: "The problem is to increase the speed of the general purpose processors, in a permanent (i.e. scalable) way." [q] The key seems to be to find a problem that a new technology solves. ie. what does my parallel array have to offer now that was not practical before. [/q] OK, I'll try - compared to conventional processors, it tries to offer more performance, achieved with parallelism. Compared to SMP systems, it tries to offer scalability. In general, it tries to offer a cell design and programming tools for processors constructed from an array of simple processing units. This was a good question, because it sets the target performance metrics for the final design (if there ever is one) - the processor is usable, when it can beat a SMP system in performance. [q] You might look to see if there is any work on computational density and heat distribution in chips. Parallel Processing Arrays should have the advantage of distributing heat dissipation, across the chip. You also have the advantage of localising high speed computational routing to small cells on the chip rather than routing data across the whole chip. [/q] The heat dissipation issue was something I haven't thought about. The high speed issue is something I have already thought about - that's the reason why I wouldn't like to use any kind of global buses inside the array. [q] To solve the distributed heat problem you need to look at how best to perform computational load balancing and the architecture of the parallel array best suited to implementing such a load balancing algorithm. [/q] True, but I probably won't put a much effort for solving that at the moment. Seems to me Douglas Adams was on the right path with "Deep Thought" The answer is 42 .... but what is the question ? ;-D What is the problem you are trying to solve with your parallel array ? Hmmh, well... The objectiveness for the project are: 1) To construct a cell design, which, when connected together to form a regular pattern array, would form a general purpose parallel processor. 2) To construct programming tools (model, languages, OS) for programming those cells to co-operatively solve computational problems, like how to save your Word document to disk. I haven't ever thought this at the point of problem-solution view, so I have some difficultiness to form the objetiveness in that way. If I now think the path, which led to this construction again, I could probably try to form it like this: "The problem is to increase the speed of the general purpose processors, in a permanent (i.e. scalable) way." The key seems to be to find a problem that a new technology solves. ie. what does my parallel array have to offer now that was not practical before. OK, I'll try - compared to conventional processors, it tries to offer more performance, achieved with parallelism. Compared to SMP systems, it tries to offer scalability. In general, it tries to offer a cell design and programming tools for processors constructed from an array of simple processing units. This was a good question, because it sets the target performance metrics for the final design (if there ever is one) - the processor is usable, when it can beat a SMP system in performance. You might look to see if there is any work on computational density and heat distribution in chips. Parallel Processing Arrays should have the advantage of distributing heat dissipation, across the chip. You also have the advantage of localising high speed computational routing to small cells on the chip rather than routing data across the whole chip. The heat dissipation issue was something I haven't thought about. The high speed issue is something I have already thought about - that's the reason why I wouldn't like to use any kind of global buses inside the array. To solve the distributed heat problem you need to look at how best to perform computational load balancing and the architecture of the parallel array best suited to implementing such a load balancing algorithm. True, but I probably won't put a much effort for solving that at the moment.

Parallel Array Processor Project by kavi on Aug 16, 2004			kavi Posts: 5 Joined: Apr 14, 2004 Last seen: Feb 27, 2020
----- Original Message ----- From: <<A HREF="http://www.opencores.org/mailman/listinfo/cores">markus at reaaliaika.net</A>> To: <<A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at opencores.org</A>> Sent: Monday, August 16, 2004 2:55 PM Subject: Re: [oc] Parallel Array Processor Project [q]> <A HREF="http://www.opencores.org/mailman/listinfo/cores">markus at r...</A> wrote: [q] > My area of intrest is MIMD and I'm very aware, that the > architecture I'm currently planning won't beat SIMD-processors > or systolic arrays in their strong area. That's not a target for > the project; the target is to design architecture and tools > for general purpose parallel processor.[/q] It is seems you clarify your application field and your expectactions. Agree. -- I don't have strong background on processor systems of MIMD-granularity, but i will comment on the following: [q] But, most of you are probably familiar with VHDL - that's one of the existing parallel languages and you probably know, that it's not impossible to make something usable with it, and it's even possible to make the code somewhat understandable, too.[/q] Well, VHDL does not adhere to any programming model! It is not a programming language, but a hardware description language, that mistake is coming up every week or so. In an HDL you just get to describe module connectivity and their internal functionalities. Of course, the VHDL notion of an event and the ability of parallel process execution (parallel in simulation time advancing) is necessary to model hardware. [q] [PicBlaze/KCPSM] [q]> For your neural network experiments, I believe that type of > implementation should suffice. Implementing a perceptron should > not take too many instructions.[/q] I think that neural nets on hardware need some more specific programmer's model. It sounds reasonable to have custom memory organization with some data structures (as constant or non-constant coefficients) allocated in scratchpad RAM, careful design of the memory interface, and maybe a coarse-grain unit in the execution stage for the given topology of the NN. The Picoblaze solution is OK if you can't spare time, need something better verified with software tools or either way could much your performance requirements. I don't expect a specialized processor for NN emulation will map efficiently on the fine-grain FPGAs. It depends on your application characteristics, too. Nikolaos Kavvadias nkavv[at]skiathos.physics.auth.gr ----- Original Message ----- From: markus at reaaliaika.net> To: cores at opencores.org> Sent: Monday, August 16, 2004 2:55 PM Subject: Re: [oc] Parallel Array Processor Project > markus at r... wrote: > My area of intrest is MIMD and I'm very aware, that the > architecture I'm currently planning won't beat SIMD-processors > or systolic arrays in their strong area. That's not a target for > the project; the target is to design architecture and tools > for general purpose parallel processor. It is seems you clarify your application field and your expectactions. Agree. -- I don't have strong background on processor systems of MIMD-granularity, but i will comment on the following: But, most of you are probably familiar with VHDL - that's one of the existing parallel languages and you probably know, that it's not impossible to make something usable with it, and it's even possible to make the code somewhat understandable, too. Well, VHDL does not adhere to any programming model! It is not a programming language, but a hardware description language, that mistake is coming up every week or so. In an HDL you just get to describe module connectivity and their internal functionalities. Of course, the VHDL notion of an event and the ability of parallel process execution (parallel in simulation time advancing) is necessary to model hardware. [PicBlaze/KCPSM] > For your neural network experiments, I believe that type of > implementation should suffice. Implementing a perceptron should > not take too many instructions. I think that neural nets on hardware need some more specific programmer's model. It sounds reasonable to have custom memory organization with some data structures (as constant or non-constant coefficients) allocated in scratchpad RAM, careful design of the memory interface, and maybe a coarse-grain unit in the execution stage for the given topology of the NN. The Picoblaze solution is OK if you can't spare time, need something better verified with software tools or either way could much your performance requirements. I don't expect a specialized processor for NN emulation will map efficiently on the fine-grain FPGAs. It depends on your application characteristics, too. Nikolaos Kavvadias nkavv[at]skiathos.physics.auth.gr

Parallel Array Processor Project by markus on Aug 16, 2004			markus Posts: 32 Joined: Dec 9, 2002 Last seen: Apr 30, 2013
[Programming array with VHDL] [q] For a large scale small cpu array, VHDL could do a great job i beleive. [/q] That's why I have borrowed many things from VHDL to my HLL. [MatrioshkaBrains] [q]> But seriously, one can imagine computer systems like that, but > how are they programmed? In which language? How are > the processing cells constructed (instruction set, memories, > external connections, etc)? > What kind of memory bus those computers have? What kind of > peripherals? [/q] I think the best model is a PC cluster. Every node contain memory and is linked to the closest other cell. Then the routing algorithm could be fractal like. [/q] Well, my design principles are: * Every node contain a memory - at least one single 8-bit result and an instruction. * Neighborhood connection: The ways to route data to distant cells is up to the software. The normal PC clusters are often topologically stars (central control) or full-connected (each node can contact any node in the cluster). [Programming array with VHDL] For a large scale small cpu array, VHDL could do a great job i beleive. That's why I have borrowed many things from VHDL to my HLL. [MatrioshkaBrains] > But seriously, one can imagine computer systems like that, but > how are they programmed? In which language? How are > the processing cells constructed (instruction set, memories, > external connections, etc)? > What kind of memory bus those computers have? What kind of > peripherals? I think the best model is a PC cluster. Every node contain memory and is linked to the closest other cell. Then the routing algorithm could be fractal like. Well, my design principles are: * Every node contain a memory - at least one single 8-bit result and an instruction. * Neighborhood connection: The ways to route data to distant cells is up to the software. The normal PC clusters are often topologically stars (central control) or full-connected (each node can contact any node in the cluster).

Parallel Array Processor Project by nico on Aug 16, 2004			nico Posts: 21 Joined: Jun 21, 2008 Last seen: May 11, 2009
[q] [Programming array with VHDL] [q] For a large scale small cpu array, VHDL could do a great job i beleive.[/q] That's why I have borrowed many things from VHDL to my HLL. [/q] Why yet a new langage ? [q] [MatrioshkaBrains] [q]> But seriously, one can imagine computer systems like that, but > how are they programmed? In which language? How are > the processing cells constructed (instruction set, memories, > external connections, etc)? > What kind of memory bus those computers have? What kind of > peripherals?[/q] I think the best model is a PC cluster. Every node contain memory and is linked to the closest other cell. Then the routing algorithm could be fractal like.[/q] Well, my design principles are: * Every node contain a memory - at least one single 8-bit result and an instruction.[/q] If it's lsome tiny cpu programmed like macro-cell of FPGA are, it must also contain all the memory code. [q] * Neighborhood connection: The ways to route data to distant cells is up to the software. [/q] So local node decide the route to an other cell. That's not the TCP/IP moto :/ The local node must be aware of the topology of the local connection. It could be really hard to make a fast routing. For fast routing, i have always seen a ring (hardwared or logical) or a switch :). [q] The normal PC clusters are often topologically stars (central control) or full-connected (each node can contact any node in the cluster).[/q] <A HREF="http://aggregate.org/KLAT2/">http://aggregate.org/KLAT2/</A> describe an other topology much more efficient and scalable. [q] _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> [/q] [Programming array with VHDL] For a large scale small cpu array, VHDL could do a great job i beleive. That's why I have borrowed many things from VHDL to my HLL. Why yet a new langage ? [MatrioshkaBrains] > But seriously, one can imagine computer systems like that, but > how are they programmed? In which language? How are > the processing cells constructed (instruction set, memories, > external connections, etc)? > What kind of memory bus those computers have? What kind of > peripherals? I think the best model is a PC cluster. Every node contain memory and is linked to the closest other cell. Then the routing algorithm could be fractal like. Well, my design principles are: * Every node contain a memory - at least one single 8-bit result and an instruction. If it's lsome tiny cpu programmed like macro-cell of FPGA are, it must also contain all the memory code. * Neighborhood connection: The ways to route data to distant cells is up to the software. So local node decide the route to an other cell. That's not the TCP/IP moto :/ The local node must be aware of the topology of the local connection. It could be really hard to make a fast routing. For fast routing, i have always seen a ring (hardwared or logical) or a switch :). The normal PC clusters are often topologically stars (central control) or full-connected (each node can contact any node in the cluster). http://aggregate.org/KLAT2/ describe an other topology much more efficient and scalable. _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

Parallel Array Processor Project by markus on Aug 16, 2004			markus Posts: 32 Joined: Dec 9, 2002 Last seen: Apr 30, 2013
[q]> > the project; the target is to design architecture > > and tools for general purpose parallel processor. [/q] It is seems you clarify your application field and your expectactions. Agree. [/q] Well, I have made some of these clarifications in my web pages, but I didn't want to "spam" them to this mailing list, too :-) Surely, the project is living and I probably need to refine the targets and designs over the time. [q]> But, most of you are probably familiar with VHDL - that's one > of the existing parallel languages and you probably know, [...][/q] Well, VHDL does not adhere to any programming model! It is not a programming language,[/q] As you can see here, I didn't say, that VHDL is a _programming_ language. It's, indeed, a parallel language in the way, that it describes the relations of concurrent events. I would use it as it is, if it would contain the structures needed for general purpose programming. [q] ...but a hardware description language, that mistake is coming up every week or so. In an HDL you just get to describe module connectivity and their internal functionalities. Of course, the VHDL notion of an event and the ability of parallel process execution (parallel in simulation time advancing) is necessary to model hardware. [/q] Yes, true and the same things are IMO necessary for a parallel programming languages, too. There's not much of those existing. The largest group of the languages used for programming parallel systems are conventional languages (C, Fortran, Pascal) with parallel "add-ons" (few instructions for synchronizing events). Mostly they are based on the message passing interface. The second largest group allows parallel execution, being still close to conventional programming languages, for example Make, LISP, Prolog and Haskell. LISP contains lot's of programming constructions, which are not possible to be executed in parallel; for example the variable model, condition checking block ("cond") and loop constructions (these can be parallelized, if you have a compiler intelligent enough - but, if you have a very intelligent compiler, every language would be parallel). Then there's a little amount of languages, which are aimed for parallel processing, for example NESL. > > the project; the target is to design architecture > > and tools for general purpose parallel processor. It is seems you clarify your application field and your expectactions. Agree. Well, I have made some of these clarifications in my web pages, but I didn't want to "spam" them to this mailing list, too :-) Surely, the project is living and I probably need to refine the targets and designs over the time. > But, most of you are probably familiar with VHDL - that's one > of the existing parallel languages and you probably know, [...] Well, VHDL does not adhere to any programming model! It is not a programming language, As you can see here, I didn't say, that VHDL is a _programming_ language. It's, indeed, a parallel language in the way, that it describes the relations of concurrent events. I would use it as it is, if it would contain the structures needed for general purpose programming. ...but a hardware description language, that mistake is coming up every week or so. In an HDL you just get to describe module connectivity and their internal functionalities. Of course, the VHDL notion of an event and the ability of parallel process execution (parallel in simulation time advancing) is necessary to model hardware. Yes, true and the same things are IMO necessary for a parallel programming languages, too. There's not much of those existing. The largest group of the languages used for programming parallel systems are conventional languages (C, Fortran, Pascal) with parallel "add-ons" (few instructions for synchronizing events). Mostly they are based on the message passing interface. The second largest group allows parallel execution, being still close to conventional programming languages, for example Make, LISP, Prolog and Haskell. LISP contains lot's of programming constructions, which are not possible to be executed in parallel; for example the variable model, condition checking block ("cond") and loop constructions (these can be parallelized, if you have a compiler intelligent enough - but, if you have a very intelligent compiler, every language would be parallel). Then there's a little amount of languages, which are aimed for parallel processing, for example NESL.

Parallel Array Processor Project by markus on Aug 16, 2004			markus Posts: 32 Joined: Dec 9, 2002 Last seen: Apr 30, 2013
[q]> That's why I have borrowed many things from VHDL to my HLL. > [/q] Why yet a new langage ? [/q] There's not many programming languages, which support low-level, fine- grained parallelism. Many of them are hard to be used for general purpose programming (e.g. APL) or they are based on sequential constructions (LISP, Prolog). The most usable programming languages are sequential (C, Pascal and alikes). [MatrioshkaBrains] [q] > I think the best model is a PC cluster. Every node contain > memory > and is linked to the closest other cell. Then the routing > algorithm could be fractal like. [/q] > > Well, my design principles are: > > * Every node contain a memory - at least one single 8-bit > result and an instruction. [/q] If it's lsome tiny cpu programmed like macro-cell of FPGA are, it must also contain all the memory code. [/q] The array itself contains the code - a single cell contains only the instruction it will execute, when fired. [q]> * Neighborhood connection: The ways to route data to distant > cells is up to the software. [/q] So local node decide the route to an other cell.[/q] Yes. [q] That's not the TCP/IP moto :/ The local node must be aware of the topology of the local connection.[/q] Well, the local node need only to move data from it's input to it's result. With the software you construct more complex routing. [q] It could be really hard to make a fast routing. [/q] True. That's why I have thought of having hardware accelerators for special purposes, like long distance data transfers. But hardware acceleration solutions are not scalable and thus they can be applied only for specific size of the array. That's why the fundamental model doesn't contain them (they are used only for HW implementations). For real world implementation, I have thought of having a hierarchial structure of the array. That means, that at the bottom, there's a processor core executing the cell instructions. They form a larger unit, and connecting these larger units you form even larger units. But I have somewhat covered those issues on my web site. [q]> The normal PC clusters are often topologically stars (central > control) or > full-connected (each node can contact any node in the > cluster). [/q] <A HREF="http://aggregate.org/KLAT2/">http://aggregate.org/KLAT2/</A> describe an other topology much more efficient and scalable. [/q] Well, yes, that's one possible hardware topology. In my design I'm still quite sceptic to use any other than neighborhood connections, for the reasons I described above. > That's why I have borrowed many things from VHDL to my HLL. > Why yet a new langage ? There's not many programming languages, which support low-level, fine- grained parallelism. Many of them are hard to be used for general purpose programming (e.g. APL) or they are based on sequential constructions (LISP, Prolog). The most usable programming languages are sequential (C, Pascal and alikes). [MatrioshkaBrains] > I think the best model is a PC cluster. Every node contain > memory > and is linked to the closest other cell. Then the routing > algorithm could be fractal like. > > Well, my design principles are: > > * Every node contain a memory - at least one single 8-bit > result and an instruction. If it's lsome tiny cpu programmed like macro-cell of FPGA are, it must also contain all the memory code. The array itself contains the code - a single cell contains only the instruction it will execute, when fired. > * Neighborhood connection: The ways to route data to distant > cells is up to the software. So local node decide the route to an other cell. Yes. That's not the TCP/IP moto :/ The local node must be aware of the topology of the local connection. Well, the local node need only to move data from it's input to it's result. With the software you construct more complex routing. It could be really hard to make a fast routing. True. That's why I have thought of having hardware accelerators for special purposes, like long distance data transfers. But hardware acceleration solutions are not scalable and thus they can be applied only for specific size of the array. That's why the fundamental model doesn't contain them (they are used only for HW implementations). For real world implementation, I have thought of having a hierarchial structure of the array. That means, that at the bottom, there's a processor core executing the cell instructions. They form a larger unit, and connecting these larger units you form even larger units. But I have somewhat covered those issues on my web site. > The normal PC clusters are often topologically stars (central > control) or > full-connected (each node can contact any node in the > cluster). http://aggregate.org/KLAT2/ describe an other topology much more efficient and scalable. Well, yes, that's one possible hardware topology. In my design I'm still quite sceptic to use any other than neighborhood connections, for the reasons I described above.

Parallel Array Processor Project by nico on Aug 16, 2004			nico Posts: 21 Joined: Jun 21, 2008 Last seen: May 11, 2009
i just read quicly your wek site. i read : "How about running redesigned 80486 with 2.8GHz clock and having one hundred of those serving your applications? " Be carefull !! A 468 with today technology should run about 200/400 Mhz even less ! What make the difference between P4 and 486 is 20 (and now 40) pipestages. The 122 Millions transistor chip of ATI (x800) run around 350 Mhz. [q]> That's why I have borrowed many things from VHDL to my HLL. >[/q] Why yet a new langage ?[/q] There's not many programming languages, which support low-level, fine- grained parallelism. Many of them are hard to be used for general purpose programming (e.g. APL) or they are based on sequential constructions (LISP, Prolog). The most usable programming languages are sequential (C, Pascal and alikes). [/q] I have heard about C + extention to use the paradigm of uniform memory adressing. [q] [MatrioshkaBrains] [q] > I think the best model is a PC cluster. Every node contain > memory > and is linked to the closest other cell. Then the routing > algorithm could be fractal like.[/q] > > Well, my design principles are: > > * Every node contain a memory - at least one single 8-bit > result and an instruction.[/q] If it's lsome tiny cpu programmed like macro-cell of FPGA are, it must also contain all the memory code.[/q] The array itself contains the code - a single cell contains only the instruction it will execute, when fired.[/q] So you will need a very very fast network to provide instruction to each cell:/ [q] [q]> * Neighborhood connection: The ways to route data to distant > cells is up to the software.[/q] So local node decide the route to an other cell.[/q] Yes. [q] That's not the TCP/IP moto :/ The local node must be aware of the topology of the local connection.[/q] Well, the local node need only to move data from it's input to it's result. With the software you construct more complex routing. [q] It could be really hard to make a fast routing.[/q] True. That's why I have thought of having hardware accelerators for special purposes, like long distance data transfers. But hardware acceleration solutions are not scalable and thus they can be applied only for specific size of the array. That's why the fundamental model doesn't contain them (they are used only for HW implementations). For real world implementation, I have thought of having a hierarchial structure of the array. That means, that at the bottom, there's a processor core executing the cell instructions. They form a larger unit, and connecting these larger units you form even larger units. [/q] The problem are the resulting bandwith could be low. [q] But I have somewhat covered those issues on my web site.[/q] i should read it better :) [q] [q]> The normal PC clusters are often topologically stars (central > control) or > full-connected (each node can contact any node in the > cluster).[/q] <A HREF="http://aggregate.org/KLAT2/">http://aggregate.org/KLAT2/</A> describe an other topology much more efficient and scalable.[/q] Well, yes, that's one possible hardware topology. In my design I'm still quite sceptic to use any other than neighborhood connections, for the reasons I described above.[/q] I beleive you will have the same problem than place & route tools for ASIC/FPGA : some time some data should be provide to hundred of cell and that could consume a lot of cell just for routing. Some data replication/modification propagation model should be used :) nicO [q] _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> [/q] i just read quicly your wek site. i read : "How about running redesigned 80486 with 2.8GHz clock and having one hundred of those serving your applications? " Be carefull !! A 468 with today technology should run about 200/400 Mhz even less ! What make the difference between P4 and 486 is 20 (and now 40) pipestages. The 122 Millions transistor chip of ATI (x800) run around 350 Mhz. > That's why I have borrowed many things from VHDL to my HLL. > Why yet a new langage ? There's not many programming languages, which support low-level, fine- grained parallelism. Many of them are hard to be used for general purpose programming (e.g. APL) or they are based on sequential constructions (LISP, Prolog). The most usable programming languages are sequential (C, Pascal and alikes). I have heard about C + extention to use the paradigm of uniform memory adressing. [MatrioshkaBrains] > I think the best model is a PC cluster. Every node contain > memory > and is linked to the closest other cell. Then the routing > algorithm could be fractal like. > > Well, my design principles are: > > * Every node contain a memory - at least one single 8-bit > result and an instruction. If it's lsome tiny cpu programmed like macro-cell of FPGA are, it must also contain all the memory code. The array itself contains the code - a single cell contains only the instruction it will execute, when fired. So you will need a very very fast network to provide instruction to each cell:/ > * Neighborhood connection: The ways to route data to distant > cells is up to the software. So local node decide the route to an other cell. Yes. That's not the TCP/IP moto :/ The local node must be aware of the topology of the local connection. Well, the local node need only to move data from it's input to it's result. With the software you construct more complex routing. It could be really hard to make a fast routing. True. That's why I have thought of having hardware accelerators for special purposes, like long distance data transfers. But hardware acceleration solutions are not scalable and thus they can be applied only for specific size of the array. That's why the fundamental model doesn't contain them (they are used only for HW implementations). For real world implementation, I have thought of having a hierarchial structure of the array. That means, that at the bottom, there's a processor core executing the cell instructions. They form a larger unit, and connecting these larger units you form even larger units. The problem are the resulting bandwith could be low. But I have somewhat covered those issues on my web site. i should read it better :) > The normal PC clusters are often topologically stars (central > control) or > full-connected (each node can contact any node in the > cluster). http://aggregate.org/KLAT2/ describe an other topology much more efficient and scalable. Well, yes, that's one possible hardware topology. In my design I'm still quite sceptic to use any other than neighborhood connections, for the reasons I described above. I beleive you will have the same problem than place & route tools for ASIC/FPGA : some time some data should be provide to hundred of cell and that could consume a lot of cell just for routing. Some data replication/modification propagation model should be used :) nicO _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

Parallel Array Processor Project by markus on Aug 16, 2004			markus Posts: 32 Joined: Dec 9, 2002 Last seen: Apr 30, 2013
[q] i read : "How about running redesigned 80486 with 2.8GHz clock and having one hundred of those serving your applications? " Be carefull !! A 468 with today technology should run about 200/400 Mhz even less ! What make the difference between P4 and 486 is 20 (and now 40) pipestages.[/q] That's why the word "redesigned" ;-) As we all know, the main reasons for the higher processor clock frequencies are new faster transistors and increased pipelines. But a simple processor core should be able to be clocked with higher frequency than a 40-stage pipelined P4. And, if the cell data width is kept in 8-bits, it should be faster than it's 32/64-bit cousins. [q] The 122 Millions transistor chip of ATI (x800) run around 350 Mhz. [/q] Yes, if the data paths inside the chip are long, you can't get high clock frequencies. [programming languages] [q] I have heard about C + extention to use the paradigm of uniform memory adressing.[/q] Yes, they do that too. [cell arrays] [q]> The array itself contains the code - a single cell contains > only the instruction it will execute, when fired. [/q] So you will need a very very fast network to provide instruction to each cell:/ [/q] I didn't quite follow this... Yes and no I need fast connections. The cells have an internal memory location to store the instruction, which is executed. During execution, it's not fetched from anywhere. My virtual memory plans requires a huge bandwidth (or let's say, that bandwidth would help a lot), when the cell number increases - but when there's enough cells, it's not needed anymore. And, meantime you can have many different virtual memory hierarchies to overcome the bandwidth problem. All in all, virtual memory requires as much bandwidth as in conventional processors, not more, not less. [q] I beleive you will have the same problem than place & route tools for ASIC/FPGA : some time some data should be provide to hundred of cell and that could consume a lot of cell just for routing.[/q] Exactly! The basic model is not optimal for SIMD-style processing, because data propagation reserves numbers of cells and it's not propagated "immediately" (but it will grantly flow inside the array). The basic model is better suited for pipelined processing (vector programming). [q] Some data replication/modification propagation model should be used :) [/q] If you want to save cells (as we probably want), yes. If you have enough of them (in the future), why bother? ;-) i read : "How about running redesigned 80486 with 2.8GHz clock and having one hundred of those serving your applications? " Be carefull !! A 468 with today technology should run about 200/400 Mhz even less ! What make the difference between P4 and 486 is 20 (and now 40) pipestages. That's why the word "redesigned" ;-) As we all know, the main reasons for the higher processor clock frequencies are new faster transistors and increased pipelines. But a simple processor core should be able to be clocked with higher frequency than a 40-stage pipelined P4. And, if the cell data width is kept in 8-bits, it should be faster than it's 32/64-bit cousins. The 122 Millions transistor chip of ATI (x800) run around 350 Mhz. Yes, if the data paths inside the chip are long, you can't get high clock frequencies. [programming languages] I have heard about C + extention to use the paradigm of uniform memory adressing. Yes, they do that too. [cell arrays] > The array itself contains the code - a single cell contains > only the instruction it will execute, when fired. So you will need a very very fast network to provide instruction to each cell:/ I didn't quite follow this... Yes and no I need fast connections. The cells have an internal memory location to store the instruction, which is executed. During execution, it's not fetched from anywhere. My virtual memory plans requires a huge bandwidth (or let's say, that bandwidth would help a lot), when the cell number increases - but when there's enough cells, it's not needed anymore. And, meantime you can have many different virtual memory hierarchies to overcome the bandwidth problem. All in all, virtual memory requires as much bandwidth as in conventional processors, not more, not less. I beleive you will have the same problem than place & route tools for ASIC/FPGA : some time some data should be provide to hundred of cell and that could consume a lot of cell just for routing. Exactly! The basic model is not optimal for SIMD-style processing, because data propagation reserves numbers of cells and it's not propagated "immediately" (but it will grantly flow inside the array). The basic model is better suited for pipelined processing (vector programming). Some data replication/modification propagation model should be used :) If you want to save cells (as we probably want), yes. If you have enough of them (in the future), why bother? ;-)

Parallel Array Processor Project by Unknown on Aug 16, 2004			Not available!
Aloha! (Going extremely off charter for the list here... ;-) Quoting <A HREF="http://www.opencores.org/mailman/listinfo/cores">markus at reaaliaika.net</A>: [q]> <A HREF="http://www.aeiveos.com/~bradbury/MatrioshkaBrains/index.html">http://www.aeiveos.com/~bradbury/MatrioshkaBrains/index.html</A>[/q] Yes, here's the goal! ;-) But seriously, one can imagine computer systems like that, but how are they programmed? In which language? How are the processing cells constructed (instruction set, memories, external connections, etc)? What kind of memory bus those computers have? What kind of peripherals?[/q] Fortunately, if Vernor Vinge is anybody to trust, by then the singularity have happened and we feeble humans have been replaced by the ancestors to the Matrioshka brains long ago. In other words: A Matrioshka brain programs itself, and since it have all the resources (energy and material) of a solar system it can probably manufacture and use any peripherial it decides it needs. Peripherials designed and manufactured from atomic level and up. ... And I guess it might use Windows for fun somewhere too, weird creatures they sure are indeed these Matrioshka brains... -- Med vÃ¤nlig hÃ¤lsning, Yours Joachim StrÃ¶mbergson - Alltid i harmonisk svÃ¤ngning. VP, Research & Development ---------------------------------------------------------------------- InformAsic AB / Hugo Grauers gata 5B / SE-411 33 GÃ–TEBORG / Sweden Tel: +46 31 68 54 90 Fax: +46 31 68 54 91 Mobile: +46 733 75 97 02 E-mail: <A HREF="http://www.opencores.org/mailman/listinfo/cores">joachim.strombergson at informasic.com</A> Home: www.informasic.com ---------------------------------------------------------------------- Aloha! (Going extremely off charter for the list here... ;-) Quoting markus at reaaliaika.net: > http://www.aeiveos.com/~bradbury/MatrioshkaBrains/index.html Yes, here's the goal! ;-) But seriously, one can imagine computer systems like that, but how are they programmed? In which language? How are the processing cells constructed (instruction set, memories, external connections, etc)? What kind of memory bus those computers have? What kind of peripherals? Fortunately, if Vernor Vinge is anybody to trust, by then the singularity have happened and we feeble humans have been replaced by the ancestors to the Matrioshka brains long ago. In other words: A Matrioshka brain programs itself, and since it have all the resources (energy and material) of a solar system it can probably manufacture and use any peripherial it decides it needs. Peripherials designed and manufactured from atomic level and up. ... And I guess it might use Windows for fun somewhere too, weird creatures they sure are indeed these Matrioshka brains... -- Med vÃ¤nlig hÃ¤lsning, Yours Joachim StrÃ¶mbergson - Alltid i harmonisk svÃ¤ngning. VP, Research & Development ---------------------------------------------------------------------- InformAsic AB / Hugo Grauers gata 5B / SE-411 33 GÃ–TEBORG / Sweden Tel: +46 31 68 54 90 Fax: +46 31 68 54 91 Mobile: +46 733 75 97 02 E-mail: joachim.strombergson at informasic.com Home: www.informasic.com ----------------------------------------------------------------------

Parallel Array Processor Project by markus on Aug 17, 2004			markus Posts: 32 Joined: Dec 9, 2002 Last seen: Apr 30, 2013
Joachim: [q] (Going extremely off charter for the list here... ;-) [/q] Well, it's just fun sometimes ;-) But I have not any additions to the "Matrioshka Brains" - it's simply the computer I would like to have at my desk. --- Me: "But a simple processor core should be able to be clocked with higher frequency than a 40-stage pipelined P4. And, if the cell data width is kept in 8-bits, it should be faster than it's 32/64-bit cousins." I of course meant, that the clock frequency of 8-bit processor should be higher than it's 32/64-bit counterparts (because of shorter propagation paths inside the processor). With the same frequency, wider processors are usually faster. --- <somewhat offtopic> Nico: "I have heard about C + extention to use the paradigm of uniform memory adressing." Have anyone programmed DSPs with C (or other higher level language)? In my other project, a DSP-based guitar effect box, I'm programming Motorola DSP56303. It's very hard to try to express variable allocation from different kinds of memories (internal/external, X/Y/P/L) and it's very hard to write a good C compiler for these. And trying to write an OS: very unpleasant job, indeed. That's why I changed back to the assembler in that project... :-) --- PicoBlaze/KCPSM: I've read the article sent by Joachim. Yes, I've thinking of constructing the array from the processors something like these. There were one idea I haven't even think about - constructing a stack- based PSM. The author has rejected this because it's not very straightforward to program, but that doesn't matter in this project. The compiler could be easily modified to output reverse polish program for the cell. In fact, it's easier to do this than make the compiler to output programs for register-based PSMs. I have tried to say in my web pages, that the compiler can be programmed to output almost any kind of code for cells - the cell can have a fixed instruction set or it can be microprogrammamble (i.e. compiler outputs code to directly access the internal muxes). Not all instructions need to be hard-coded for the cell; microprogrammable cell can be programmed to perform more complex operations, like multiplication. The compiler can utilize the cells even more - it can collect parts of the software (for example, short equations, iterative loops) and convert those to be executed in one cell. The stack-based PSM would have a very dense instruction set and it would be versatile with small efforts. Certainly I have think about this more closely. Joachim: (Going extremely off charter for the list here... ;-) Well, it's just fun sometimes ;-) But I have not any additions to the "Matrioshka Brains" - it's simply the computer I would like to have at my desk. --- Me: "But a simple processor core should be able to be clocked with higher frequency than a 40-stage pipelined P4. And, if the cell data width is kept in 8-bits, it should be faster than it's 32/64-bit cousins." I of course meant, that the clock frequency of 8-bit processor should be higher than it's 32/64-bit counterparts (because of shorter propagation paths inside the processor). With the same frequency, wider processors are usually faster. --- Nico: "I have heard about C + extention to use the paradigm of uniform memory adressing." Have anyone programmed DSPs with C (or other higher level language)? In my other project, a DSP-based guitar effect box, I'm programming Motorola DSP56303. It's very hard to try to express variable allocation from different kinds of memories (internal/external, X/Y/P/L) and it's very hard to write a good C compiler for these. And trying to write an OS: very unpleasant job, indeed. That's why I changed back to the assembler in that project... :-) --- PicoBlaze/KCPSM: I've read the article sent by Joachim. Yes, I've thinking of constructing the array from the processors something like these. There were one idea I haven't even think about - constructing a stack- based PSM. The author has rejected this because it's not very straightforward to program, but that doesn't matter in this project. The compiler could be easily modified to output reverse polish program for the cell. In fact, it's easier to do this than make the compiler to output programs for register-based PSMs. I have tried to say in my web pages, that the compiler can be programmed to output almost any kind of code for cells - the cell can have a fixed instruction set or it can be microprogrammamble (i.e. compiler outputs code to directly access the internal muxes). Not all instructions need to be hard-coded for the cell; microprogrammable cell can be programmed to perform more complex operations, like multiplication. The compiler can utilize the cells even more - it can collect parts of the software (for example, short equations, iterative loops) and convert those to be executed in one cell. The stack-based PSM would have a very dense instruction set and it would be versatile with small efforts. Certainly I have think about this more closely.

First

Prev

2/5

Next

Last

© copyright 1999-2026 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.