If anybody has radix-2 FFT (8 or 16 point), please contact through jayesh_parmar@in.com
Im in great need.
thanx in advance

Hi
even i do require it but i want the FFT in parallel
ie all the inputs to be fed in parallel.
let it be area consuming.
but i will send all the samples in parallel and get the output parallel

thanks in advance
prasad
kdnvsprasad@bel.co.in

You can try http://www.altera.com/support/examples/verilog/ver-fft-32k.html

but it won't be a simple code. If you want some reference material for coding one yourself, try this algorithms coding book:
http://www.jjj.de/fxt/fxtbook.pdf

hi... I too need an radix 2 8 point FFT code. can anyone help me.

I suppose you could implement each FFT bin using a CORDIC followed by a block average.

Is this what you want to do?

The more I think of this request, the less sense it makes to me. If you consider the output of one bin of an FFT, the bandwidth at the output of the block averaging stage is such that you can easily decimate without any loss of information. One common decimation would be the FFT length over two. Then, from this newly resampled stream, you can also still reconstruct the incoming stream with no loss of information. (Decimation by the FFT length will result in aliasing products ...)

So, while I find the request interesting, calculating a new FFT for every input sample just doesn't seem to make any practical sense.

Please feel free to disagree with me if you think I am missing something.

sir,
i did fft code but i am not sure which is write or not. please could you help me if it is not correct . i have attached my code given below. please anybody correct the code and send to this mail id- janakitece@gmail.com

thanks in advance

Janapriya,

I took a look over your code and ... I would suggest you head back to the drawing board. No offense, but the Verilog language has some very rich constructs that should keep you from needing to define a0-a31, ai0-ai31, and so forth. Even better, should you use these constructs, your code will be easier to read and understand--and it would thence be easier on my part to tell if you've got it right or not based upon little more than a fairly cursory read.

Another question might be, how do you intend to test your core? Have you looked into Verilator? The last time I worked on an FFT implementation in Verilog, I had Verilator simulate the Verilog and used a GNOME front end to plot the results. You might try matlab, octave, or gnuplot as alternatives to plotting the results. If you've built your core properly, you should be able to watch tones that you input into your core produce impulses on the back end.

While it's not perfect, there are some test functions in the Double Clocked FFT core that you might find valuable. Check out the fft_tb.cpp file in the trunk/bench/cpp directory and see if that helps you out at all.

Dan

After a longer look, no, you don't have it. 8-pt FFT's and beyond require multiplies, and I couldn't find any multiplies in your code.

I also notice that you are thinking like a computer programmer. FPGA development is substantially different from your standard computer programming. Internal to an FPGA, everything is done at once--not sequentially. That parallelism is what makes FPGA's unique, special, and fun to work with.

Before saying much more, I think we've let this discussion thread lose focus. Can you define just what it is you are trying to do? Your routine header offers no inputs, one complex output, and a clock. This doesn't match an appropriate header for any FFT implementation that I know of.

Hopefully this helps,

Dan