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translate state diagram to VHDL code
by ravi12355 on Oct 13, 2009 |
ravi12355
Posts: 3 Joined: Oct 11, 2009 Last seen: Jan 7, 2010 |
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I am providing the state diagrams of a GPIB controller. I need the VHDL code for all the state diagrams and interaction between them. so could anyone please provide me translated VHDL code from a given state diagram.
gpib state diagrams.doc (151 kb)
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RE: translate state diagram to VHDL code
by fpga_is_funny on Oct 13, 2009 |
fpga_is_funny
Posts: 3 Joined: Dec 13, 2006 Last seen: Oct 12, 2026 |
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Hi
I can do this for you. First, I have some questions: 1. "pon" means "Power On"? 2. Do you have some special requirements for speed, encoding or fail safe FSM? It is possible to finish this work until next week (around Oct 23th) Awaiting your response Best Regards Jens Gutschmidt |
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RE: translate state diagram to VHDL code
by ranjith.b on Oct 14, 2009 |
ranjith.b
Posts: 1 Joined: Oct 13, 2009 Last seen: Mar 7, 2010 |
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no speed requirements
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RE: translate state diagram to VHDL code
by ravi12355 on Oct 14, 2009 |
ravi12355
Posts: 3 Joined: Oct 11, 2009 Last seen: Jan 7, 2010 |
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yes pon means power on. I dont have certain specifications. Implement it using your own specification and please send it to me.
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RE: translate state diagram to VHDL code
by fpga_is_funny on Oct 27, 2009 |
fpga_is_funny
Posts: 3 Joined: Dec 13, 2006 Last seen: Oct 12, 2026 |
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Hello
The first version is ready for review. Please contact me via scantara2003@yahoo.de directly. There are still some questions about the state maschines because the document "1255453451_gpib state diagrams.doc" describes only the states and the transitions between them. But there are no actions defined. So finally in the first version every state has its own output wire to activate external actions. Please note that state "ANAS" on page 2 is unreachable! I assume that some informations you gave to me are incomplete or incorrect. Best Regards Jens Gutschmidt |
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