Hi I have a query regarding VERA. Is it possible to connect a variable defined in a class to be connected to a port defined in the interface (.if.vrh) file. example: i have a class in which a variable rst has been declared as a bit. the reset is being pulled high @(posedge CLOCK). i also have a hdl from which i have a generated a if.vrh file which has a port called reset. I want to connect the variable rst to the port reset. this is especially critical to me because i want to generate all the stimulus inside a class and then plug in this class and test the hdl. final objective is reusability. thanks and regards Unmesh Khadilkar -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20040730/502fcd0d/attachment.htm