Hi all, I tried to send this message yesterday but never got it back, so here's one more try. I apologise in advance for any duplicates. Paul Message-ID: 41081C3B.7040904 at colony.mit.edu> Date: Wed, 28 Jul 2004 17:35:55 -0400 From: "Paul T. Pham" ppham at colony.mit.edu> User-Agent: Mozilla Thunderbird 0.7.2 (Windows/20040707) X-Accept-Language: en-us, en MIME-Version: 1.0 To: cores at opencores.org Subject: VHDL TCP/IP stack Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Hi all, I am currently working on a TCP/IP stack in VHDL that I would like to contribute to OpenCores under LGPL. If anyone knows of similar efforts or past discussions, I would appreciate pointers. The only free/academic project I know of is Ashley Partis and Jorgen Peddersen at the University of Queensland: http://www.itee.uq.edu.au/~peters/xsvboard/ However, I am trying to construct as many of the individual modules to be Wishbone compliant, so they can be swapped out or improved upon independently. I know there is a fully-functional and tested Ethernet MAC in Verilog by Igor Mohor already on OpenCores, but I don't know Verilog very well and I was hoping to teach myself more about low-level networking the hard way. A first question: To implement buffers and lookup tables, I am currently using completely behavioural descriptions with arrays of std_logic_vector and letting my synthesis tool (Altera's Quartus) infer the use of built-in FPGA RAM blocks. This seems more portable and faster to me than using an external SRAM interface, which has to be multiplexed among other cores. Does anyone have an opinion or advice for or against this approach? Many thanks, Paul _______________________________________________ http://www.opencores.org/mailman/listinfo/cores