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ip cores implementation in xilix fpga

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ip cores implementation in xilix fpga by Unknown on Aug 9, 2004			Not available!
hi everyone, I'm new to this kind of chips. I have work with many processor type and different hardware types. Now is the time to use fpga in our design. I have discover opencores. Wow I find here everything i need to make my design. The only problem I have some difficulty to understand the way how module are connected together. Whisbone is a soc bus. But i need a little tutorial to get started. I see the one in OpenRisk but this one isn't done for ise from xilinx. My Hardware is the spartant3 from xilinx. ise webpack. I have done oone program (a simple and gate) and download it to the spartant and i understand the process to get a code running in the spartant. So i only need a little more info on how to use opencores in ise. and how should i connect the wishbone bus. regards Jonathan hi everyone, I'm new to this kind of chips. I have work with many processor type and different hardware types. Now is the time to use fpga in our design. I have discover opencores. Wow I find here everything i need to make my design. The only problem I have some difficulty to understand the way how module are connected together. Whisbone is a soc bus. But i need a little tutorial to get started. I see the one in OpenRisk but this one isn't done for ise from xilinx. My Hardware is the spartant3 from xilinx. ise webpack. I have done oone program (a simple and gate) and download it to the spartant and i understand the process to get a code running in the spartant. So i only need a little more info on how to use opencores in ise. and how should i connect the wishbone bus. regards Jonathan

ip cores implementation in xilix fpga by Unknown on Aug 10, 2004			Not available!
-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On Tuesday 10 August 2004 03:09, jonathan dumaresq wrote: [q] hi everyone, I'm new to this kind of chips. I have work with many processor type and different hardware types. Now is the time to use fpga in our design. I have discover opencores. Wow I find here everything i need to make my design. The only problem I have some difficulty to understand the way how module are connected together. Whisbone is a soc bus. But i need a little tutorial to get started. I see the one in OpenRisk but this one isn't done for ise from xilinx. [/q] OpenRISC compiles nicely in ISE and is implementable on Xilinx.. This is using the source code downloaded directly from the site.. You just need to get rid of cache memory to reduce the size.. But I'm not sure if it'll fit into a Spartan3.. It should run around 25MHz or so... [q] My Hardware is the spartant3 from xilinx. ise webpack. I have done oone program (a simple and gate) and download it to the spartant and i understand the process to get a code running in the spartant.[/q] Great that you can get the basic flow to work.. Now you can go on to bigger tasks.. [q] So i only need a little more info on how to use opencores in ise. and how should i connect the wishbone bus.[/q] For the Wishbone bus, read up the wishbone 3 spec here: <A HREF="http://www.opencores.org/projects.cgi/web/wishbone/wbspec_b3.pdf">http://www.opencores.org/projects.cgi/web/wishbone/wbspec_b3.pdf</A> Some of the cores only adhere to the legacy portion of the specifications while others are WB2.. Once you can understand the bus architecture, connecting various cores together is just about writing a top level block that wires up all the other blocks together... - -- with metta, Shawn Tan -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.2.4 (GNU/Linux) iD8DBQFBGBdQUgUYbQRKphMRAqJFAJ4t+qL97MgBrJKZdXsnO1uoutoAbgCgkqXo 0BIia+vuVwospZapzwGniRM= =uVBX -----END PGP SIGNATURE----- -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On Tuesday 10 August 2004 03:09, jonathan dumaresq wrote: hi everyone, I'm new to this kind of chips. I have work with many processor type and different hardware types. Now is the time to use fpga in our design. I have discover opencores. Wow I find here everything i need to make my design. The only problem I have some difficulty to understand the way how module are connected together. Whisbone is a soc bus. But i need a little tutorial to get started. I see the one in OpenRisk but this one isn't done for ise from xilinx. OpenRISC compiles nicely in ISE and is implementable on Xilinx.. This is using the source code downloaded directly from the site.. You just need to get rid of cache memory to reduce the size.. But I'm not sure if it'll fit into a Spartan3.. It should run around 25MHz or so... My Hardware is the spartant3 from xilinx. ise webpack. I have done oone program (a simple and gate) and download it to the spartant and i understand the process to get a code running in the spartant. Great that you can get the basic flow to work.. Now you can go on to bigger tasks.. So i only need a little more info on how to use opencores in ise. and how should i connect the wishbone bus. For the Wishbone bus, read up the wishbone 3 spec here: http://www.opencores.org/projects.cgi/web/wishbone/wbspec_b3.pdf Some of the cores only adhere to the legacy portion of the specifications while others are WB2.. Once you can understand the bus architecture, connecting various cores together is just about writing a top level block that wires up all the other blocks together... - -- with metta, Shawn Tan -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.2.4 (GNU/Linux) iD8DBQFBGBdQUgUYbQRKphMRAqJFAJ4t+qL97MgBrJKZdXsnO1uoutoAbgCgkqXo 0BIia+vuVwospZapzwGniRM= =uVBX -----END PGP SIGNATURE-----

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