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Verilog Z80?
by Unknown on Aug 11, 2004 |
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Hi - I'm looking for a Z80 in Verilog (it has to be Verilog [or SystemC]
because I need to talk to the core using a PLI of some sort, and I don't know of any cheap/free VHDL sims with PLI/FLI functionality). Any ideas? I've downloaded wb_z80 but, after a little while looking at it, I have some concerns. The main problem is that it has an interesting BIST for testing, but I'd prefer a raw Zilog-compatible core so that I can do my own testing. The docs are also a bit thin (sorry!), and it appears to have some DOS requirement (I'm on Linux). Cheers - Richard |
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Verilog Z80?
by bporcella on Aug 11, 2004 |
bporcella
Posts: 22 Joined: Jan 16, 2004 Last seen: Oct 2, 2007 |
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Richard:
Just to clarify.
The BIST is trivial to remove. Doing your own testing with PLI is straightforward.
If you want the Zilog pinout rather than the Wishbone, I guess that's a minor problem (but I don't see that it has
anything to do with testing).
The docs Are thin - but then what do you want for free :-).
There is no DOS requirement. The build script runs on DOS -- but if you can read pearl - it should be pretty easy to
convert to any OS and tool set.
There is also a tv_80 core (a verilog conversion from the t_80) in verilog that you might look at.
bj Porcella
http://pages.sbcglobal.net/bporcella/
----- Original Message -----
From: "Richard Tierney" mfoc73 at dsl.pipex.com>
To: cores at opencores.org>
Sent: Wednesday, August 11, 2004 2:41 AM
Subject: [oc] Verilog Z80?
Hi - I'm looking for a Z80 in Verilog (it has to be Verilog [or SystemC]
because I need to talk to the core using a PLI of some sort, and I don't
know of any cheap/free VHDL sims with PLI/FLI functionality).
Any ideas? I've downloaded wb_z80 but, after a little while looking at
it, I have some concerns. The main problem is that it has an interesting
BIST for testing, but I'd prefer a raw Zilog-compatible core so that I
can do my own testing. The docs are also a bit thin (sorry!), and it
appears to have some DOS requirement (I'm on Linux).
Cheers -
Richard
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores
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Verilog Z80?
by Unknown on Aug 11, 2004 |
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Richard,
Check out the TV80 core. It's a Verilog port of the T80. I'm still putting together a full verification suite, but so far the testing hasn't turned up any incompatibilities. Verification all done on Linux using CVer. - Guy |
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Verilog Z80?
by Unknown on Aug 11, 2004 |
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bporcella wrote:
Richard:
Just to clarify. The BIST is trivial to remove. Doing your own testing with PLI is straightforward. If you want the Zilog pinout rather than the Wishbone, I guess that's a minor problem (but I don't see that it has anything to do with testing). The docs Are thin - but then what do you want for free :-). There is no DOS requirement. The build script runs on DOS -- but if you can read pearl - it should be pretty easy to convert to any OS and tool set. Thanks - I'll have another look and give it a go. I don't need a Zilog pinout, so that's not a problem.
There is also a tv_80 core (a verilog conversion from the t_80) in verilog that you might look at.
Interesting. As far as I can see, there are no links to tv80 from the
front-end of opencores; I had to find it on google, which gave me
http://www.opencores.org/projects.cgi/web/tv80/overview>. It also came
up with a posting from this list
(http://www.opencores.org/forums.cgi/cores/2004/07/000984), which
doesn't give me a nice warm feeling.. :(
Cheers
Richard
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Verilog Z80?
by Unknown on Aug 11, 2004 |
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Guy Hutchison wrote:
Richard,
Check out the TV80 core. It's a Verilog port of the T80. I'm still putting together a full verification suite, but so far the testing hasn't turned up any incompatibilities. Verification all done on Linux using CVer. Thanks Guy - I've just downloaded it. I've got my own verification code, so I'll try to give both cores a go. Cheers Richard |
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Verilog Z80?
by Unknown on Aug 11, 2004 |
Not available! | ||
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Interesting. As far as I can see, there are no links to tv80 from the
front-end of opencores; I had to find it on google, which gave me
http://www.opencores.org/projects.cgi/web/tv80/overview>.
I haven't figured out how to change the status of the core. I believe it won't show up unless the status is "complete".
It also came
up with a posting from this list
(http://www.opencores.org/forums.cgi/cores/2004/07/000984), which
doesn't give me a nice warm feeling.. :(
I never got any details on this problem. The problem report was that it was completely broken, and I happen to know it's not, so I suspected user error, and replied as such. - Guy |
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Verilog Z80?
by Unknown on Aug 11, 2004 |
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On Wed, 11 Aug 2004 16:05:37 +0100, Richard Tierney
mfoc73 at dsl.pipex.com> wrote:
Guy Hutchison wrote:
> Richard,
> > Check out the TV80 core. It's a Verilog port of the T80. I'm still > putting together a full verification suite, but so far the testing > hasn't turned up any incompatibilities. Verification all done on > Linux using CVer. Thanks Guy - I've just downloaded it. I've got my own verification code, so I'll try to give both cores a go. No problem. Please let me know what you turn up. - Guy |
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